[DAGCombine] Don't fold a trunc if it feeds an anyext

[mkuper]

Summary

Legalization tends to create anyext(trunc) patterns. This should always be combined - into either a single trunc, a single ext, or nothing if the types match exactly. But if we happen to combine the trunc first, we may pull the trunc away from the anyext or make it implicit (e.g. the truncate(extract) -> extract(bitcast) fold). To prevent this, we can avoid doing the fold, similarly to how we already handle fpround(fpextend).

This is somewhat ugly, but the alternative is to try to undo this later when we combine the anyext, and that gets painful.

[RKSimon]

Are the mem-intrin-base-reg.ll changes relevant?

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7139

Should we limit this to AfterLegalizeTypes or later?

[mkuper]

In D23893#525962, @RKSimon wrote:

Are the mem-intrin-base-reg.ll changes relevant?

Surprisingly, yes.

The test was documented to use a vector pattern to create an "aligned temporary" from the vector compare and extract.
We used to generate:

pcmpgtd %xmm1, %xmm0
movdqa  %xmm0, 32(%esp)
movzbl  32(%esp), %eax
andl    $1, %eax

With this patch, we no longer have the temporary - we now get:

pcmpgtd %xmm1, %xmm0
movd    %xmm0, %eax
andl    $1, %eax

This is clearly better - but the temporary at 32(%esp) is gone.
The alloca forces the stack back into alignment.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7139

My motivation for this was a situation that occurs post-legalization, but I don't see anything specific to being post-legalization that makes this a good (or bad) idea.
Why do you think we should limit this?

[RKSimon]

LGTM

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7139

I was trying to think if there were any cases where it should be reduced, but you're right it will be from legalization anyhow.

test/CodeGen/X86/2011-10-21-widen-cmp.ll

18

This code still makes me shudder, but its a job for another day.....

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N0.getOpcode() == ISD::ZERO_EXTEND ||
     // if the source is larger than the dest, than we just need the truncate.
     if (N0.getOperand(0).getValueType().bitsGT(VT))
       return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
     // if the source and dest are the same type, we can drop both the extend
     // and the truncate.
     return N0.getOperand(0);
   }
 
+  // If this is anyext(trunc), don't fold it, allow ourselves to be folded.
+  if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND))
+    return SDValue();
+
   // Fold extract-and-trunc into a narrow extract. For example:
   //   i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
   //   i32 y = TRUNCATE(i64 x)
   //        -- becomes --
   //   v16i8 b = BITCAST (v2i64 val)
   //   i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
   //
   // Note: We only run this optimization after type legalization (which often

test/CodeGen/X86/2011-10-21-widen-cmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
 
 ; Check that a <4 x float> compare is generated and that we are
 ; not stuck in an endless loop.
 
 define void @cmp_2_floats() {
 ; CHECK-LABEL: cmp_2_floats:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    cmpordps %xmm0, %xmm0
 ; CHECK-NEXT:    pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
 ; CHECK-NEXT:    psllq $32, %xmm0
-; CHECK-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; CHECK-NEXT:    psrad $31, %xmm0
-; CHECK-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
-; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
 ; CHECK-NEXT:    pslld $31, %xmm0
 ; CHECK-NEXT:    blendvps %xmm0, %xmm0
 ; CHECK-NEXT:    movlps %xmm0, (%rax)
 ; CHECK-NEXT:    retq
 entry:
   %0 = fcmp oeq <2 x float> undef, undef
   %1 = select <2 x i1> %0, <2 x float> undef, <2 x float> undef
   store <2 x float> %1, <2 x float>* undef
   ret void
 }
 
 define void @cmp_2_doubles() {
 ; CHECK-LABEL: cmp_2_doubles:

test/CodeGen/X86/mem-intrin-base-reg.ll

 ; RUN: llc -mtriple=i686-windows -mattr=+sse2 < %s | FileCheck %s
 
 target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
 target triple = "i686-pc-windows-msvc"
 
 ; There is a conflict between lowering the X86 memory intrinsics and the "base"
 ; register used to address stack locals.  See X86RegisterInfo::hasBaseRegister
 ; for when this is necessary. Typically, we chose ESI for the base register,
 ; which all of the X86 string instructions use.
 
-; The pattern of vector icmp and extractelement is used in these tests because
-; it forces creation of an aligned stack temporary. Perhaps such temporaries
-; shouldn't be aligned.
-
 declare void @escape_vla_and_icmp(i8*, i1 zeroext)
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1)
 declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1)
 
 define i32 @memcpy_novla_vector(<4 x i32>* %vp0, i8* %a, i8* %b, i32 %n, i1 zeroext %cond) {
+  %foo = alloca <4 x i32>, align 16
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 128, i32 4, i1 false)
   br i1 %cond, label %spill_vectors, label %no_vectors
 
 no_vectors:
   ret i32 0
 
 spill_vectors:
   %vp1 = getelementptr <4 x i32>, <4 x i32>* %vp0, i32 1

 ; CHECK-LABEL: _memcpy_novla_vector:
 ; CHECK: andl $-16, %esp
 ; CHECK-DAG: movl $32, %ecx
 ; CHECK-DAG: movl {{.*}}, %esi
 ; CHECK-DAG: movl {{.*}}, %edi
 ; CHECK: rep;movsl
 
 define i32 @memcpy_vla_vector(<4 x i32>* %vp0, i8* %a, i8* %b, i32 %n, i1 zeroext %cond) {
+  %foo = alloca <4 x i32>, align 16
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 128, i32 4, i1 false)
   br i1 %cond, label %spill_vectors, label %no_vectors
 
 no_vectors:
   ret i32 0
 
 spill_vectors:
   %vp1 = getelementptr <4 x i32>, <4 x i32>* %vp0, i32 1

 ; CHECK: movl %esp, %esi
 ; CHECK: pushl $128
 ; CHECK: calll _memcpy
 ; CHECK: calll __chkstk
 
 ; stosd doesn't clobber esi, so we can use it.
 
 define i32 @memset_vla_vector(<4 x i32>* %vp0, i8* %a, i32 %n, i1 zeroext %cond) {
+  %foo = alloca <4 x i32>, align 16
   call void @llvm.memset.p0i8.i32(i8* %a, i8 42, i32 128, i32 4, i1 false)
   br i1 %cond, label %spill_vectors, label %no_vectors
 
 no_vectors:
   ret i32 0
 
 spill_vectors:
   %vp1 = getelementptr <4 x i32>, <4 x i32>* %vp0, i32 1