MachineScheduler: Add constructor functions for the DAGMutations

[• tstellarAMD]

Summary

This way they can be re-used by target-specific schedulers.

[MatzeB]

Do you actually need the full declaration in the header or would it be enough to provide constructor functions?

[• tstellarAMD]

In D23678#519794, @MatzeB wrote:

Do you actually need the full declaration in the header or would it be enough to provide constructor functions?

Constructor functions would be fine.

[• tstellarAMD]

Use constructor functions.

[MatzeB]

LGTM. If possible please also change the code inside MachineScheduler.cpp to use the new functions!

[kparzysz]

include/llvm/CodeGen/MachineScheduler.h

1069

Can these types be identical for all the constructors?

[• tstellarAMD]

Use new constructors in MachineScheduler.cpp and make arguments consistent.

include/llvm/CodeGen/MachineScheduler.h

protected:
   void initRegPressure();
 
   void updatePressureDiffs(ArrayRef<RegisterMaskPair> LiveUses);
 
   void updateScheduledPressure(const SUnit *SU,
                                const std::vector<unsigned> &NewMaxPressure);
 };
 
+/// \brief Post-process the DAG to create cluster edges between neighboring
+/// loads or between neighboring stores.
+class BaseMemOpClusterMutation : public ScheduleDAGMutation {
+  struct MemOpInfo {
+    SUnit *SU;
+    unsigned BaseReg;
+    int64_t Offset;
+    MemOpInfo(SUnit *su, unsigned reg, int64_t ofs)
+        : SU(su), BaseReg(reg), Offset(ofs) {}
+
+    bool operator<(const MemOpInfo&RHS) const {
+      return std::tie(BaseReg, Offset) < std::tie(RHS.BaseReg, RHS.Offset);
+    }
+  };
+
+  const TargetInstrInfo *TII;
+  const TargetRegisterInfo *TRI;
+  bool IsLoad;
+
+public:
+  BaseMemOpClusterMutation(const TargetInstrInfo *tii,
+                           const TargetRegisterInfo *tri, bool IsLoad)
+      : TII(tii), TRI(tri), IsLoad(IsLoad) {}
+
+  void apply(ScheduleDAGInstrs *DAGInstrs) override;
+
+protected:
+  void clusterNeighboringMemOps(ArrayRef<SUnit *> MemOps, ScheduleDAGMI *DAG);
+};
+
+class StoreClusterMutation : public BaseMemOpClusterMutation {
+public:
+  StoreClusterMutation(const TargetInstrInfo *tii,
+                       const TargetRegisterInfo *tri)
+      : BaseMemOpClusterMutation(tii, tri, false) {}
+};
+
+class LoadClusterMutation : public BaseMemOpClusterMutation {
+public:
+  LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri)
+      : BaseMemOpClusterMutation(tii, tri, true) {}
+};
+
+/// \brief Post-process the DAG to create weak edges from all uses of a copy to
+/// the one use that defines the copy's source vreg, most likely an induction
+/// variable increment.
+class CopyConstrain : public ScheduleDAGMutation {
+  // Transient state.
+  SlotIndex RegionBeginIdx;
+  // RegionEndIdx is the slot index of the last non-debug instruction in the
+  // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
+  SlotIndex RegionEndIdx;
+public:
+  CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
+
+  void apply(ScheduleDAGInstrs *DAGInstrs) override;
+
+protected:
+  void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
+};
+
 //===----------------------------------------------------------------------===//
 ///
 /// Helpers for implementing custom MachineSchedStrategy classes. These take
 /// care of the book-keeping associated with list scheduling heuristics.
 ///
 //===----------------------------------------------------------------------===//
 
 /// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience

 protected:
   void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand);
 
   void pickNodeFromQueue(SchedCandidate &Cand);
 };
 
 } // namespace llvm
 
 #endif

lib/CodeGen/MachineScheduler.cpp

if (IsTopNode) {
     }
   }
 }
 
 //===----------------------------------------------------------------------===//
 // BaseMemOpClusterMutation - DAG post-processing to cluster loads or stores.
 //===----------------------------------------------------------------------===//
 
-namespace {
-/// \brief Post-process the DAG to create cluster edges between neighboring
-/// loads or between neighboring stores.
-class BaseMemOpClusterMutation : public ScheduleDAGMutation {
-  struct MemOpInfo {
-    SUnit *SU;
-    unsigned BaseReg;
-    int64_t Offset;
-    MemOpInfo(SUnit *su, unsigned reg, int64_t ofs)
-        : SU(su), BaseReg(reg), Offset(ofs) {}
-
-    bool operator<(const MemOpInfo&RHS) const {
-      return std::tie(BaseReg, Offset) < std::tie(RHS.BaseReg, RHS.Offset);
-    }
-  };
-
-  const TargetInstrInfo *TII;
-  const TargetRegisterInfo *TRI;
-  bool IsLoad;
-
-public:
-  BaseMemOpClusterMutation(const TargetInstrInfo *tii,
-                           const TargetRegisterInfo *tri, bool IsLoad)
-      : TII(tii), TRI(tri), IsLoad(IsLoad) {}
-
-  void apply(ScheduleDAGInstrs *DAGInstrs) override;
-
-protected:
-  void clusterNeighboringMemOps(ArrayRef<SUnit *> MemOps, ScheduleDAGMI *DAG);
-};
-
-class StoreClusterMutation : public BaseMemOpClusterMutation {
-public:
-  StoreClusterMutation(const TargetInstrInfo *tii,
-                       const TargetRegisterInfo *tri)
-      : BaseMemOpClusterMutation(tii, tri, false) {}
-};
-
-class LoadClusterMutation : public BaseMemOpClusterMutation {
-public:
-  LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri)
-      : BaseMemOpClusterMutation(tii, tri, true) {}
-};
-} // anonymous
-
 void BaseMemOpClusterMutation::clusterNeighboringMemOps(
     ArrayRef<SUnit *> MemOps, ScheduleDAGMI *DAG) {
   SmallVector<MemOpInfo, 32> MemOpRecords;
   for (unsigned Idx = 0, End = MemOps.size(); Idx != End; ++Idx) {
     SUnit *SU = MemOps[Idx];
     unsigned BaseReg;
     int64_t Offset;
     if (TII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseReg, Offset, TRI))
for (SUnit &SU : DAG->SUnits) {
     break;
   }
 }
 
 //===----------------------------------------------------------------------===//
 // CopyConstrain - DAG post-processing to encourage copy elimination.
 //===----------------------------------------------------------------------===//
 
-namespace {
-/// \brief Post-process the DAG to create weak edges from all uses of a copy to
-/// the one use that defines the copy's source vreg, most likely an induction
-/// variable increment.
-class CopyConstrain : public ScheduleDAGMutation {
-  // Transient state.
-  SlotIndex RegionBeginIdx;
-  // RegionEndIdx is the slot index of the last non-debug instruction in the
-  // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
-  SlotIndex RegionEndIdx;
-public:
-  CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
-
-  void apply(ScheduleDAGInstrs *DAGInstrs) override;
-
-protected:
-  void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
-};
-} // anonymous
-
 /// constrainLocalCopy handles two possibilities:
 /// 1) Local src:
 /// I0:     = dst
 /// I1: src = ...
 /// I2:     = dst
 /// I3: dst = src (copy)
 /// (create pred->succ edges I0->I1, I2->I1)
 ///