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AMDGPU: Mark sched model complete
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Authored by arsenm on Aug 17 2016, 8:32 PM.

Reviewers

• tstellarAMD

Summary

Fixes bug 26800

arsenm retitled this revision from to AMDGPU: Mark sched model complete.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

LGTM.

This revision is now accepted and ready to land.Aug 26 2016, 5:35 PM

r279910

Path

Size

lib/

Target/

AMDGPU/

2 lines

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	// Half rate 64-bit instructions.			// Half rate 64-bit instructions.
	def Write64Bit : SchedWrite;			def Write64Bit : SchedWrite;

	// FIXME: Should there be a class for instructions which are VALU			// FIXME: Should there be a class for instructions which are VALU
	// instructions and have VALU rates, but write to the SALU (i.e. VOPC			// instructions and have VALU rates, but write to the SALU (i.e. VOPC
	// instructions)			// instructions)

	class SISchedMachineModel : SchedMachineModel {			class SISchedMachineModel : SchedMachineModel {
	let CompleteModel = 0;			let CompleteModel = 1;
	let IssueWidth = 1;			let IssueWidth = 1;
	let PostRAScheduler = 1;			let PostRAScheduler = 1;
	}			}

	def SIFullSpeedModel : SISchedMachineModel;			def SIFullSpeedModel : SISchedMachineModel;
	def SIQuarterSpeedModel : SISchedMachineModel;			def SIQuarterSpeedModel : SISchedMachineModel;

	// XXX: Are the resource counts correct?			// XXX: Are the resource counts correct?
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