Tests: Add branch weights to non-layout tests.

[iteratee]

Summary

Add branch weights to a few tests that aren't testing layout to make them less
sensitive to changes in the layout algorithm.

[davidxl]

this makes the tests more robust -- LGTM

test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll

 ; RUN: llc -O1 -mtriple=arm64-apple-ios7.0.0 -enable-andcmp-sinking=true < %s | FileCheck %s
 ; ModuleID = 'and-cbz-extr-mr.bc'
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
 
 define zeroext i1 @foo(i1 %IsEditable, i1 %isTextField, i8* %str1, i8* %str2, i8* %str3, i8* %str4, i8* %str5, i8* %str6, i8* %str7, i8* %str8, i8* %str9, i8* %str10, i8* %str11, i8* %str12, i8* %str13, i32 %int1, i8* %str14) unnamed_addr #0 align 2 {
 ; CHECK: _foo:
 entry:
   %tobool = icmp eq i8* %str14, null
   br i1 %tobool, label %return, label %if.end
 
 ; CHECK: %if.end
 ; CHECK: tbz
 if.end:                                           ; preds = %entry
   %and.i.i.i = and i32 %int1, 4
   %tobool.i.i.i = icmp eq i32 %and.i.i.i, 0
-  br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i
+  br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i, !prof !1
 
 land.rhs.i:                                       ; preds = %if.end
   %cmp.i.i.i = icmp eq i8* %str12, %str13
   br i1 %cmp.i.i.i, label %if.then3, label %lor.rhs.i.i.i
 
 lor.rhs.i.i.i:                                    ; preds = %land.rhs.i
   %cmp.i13.i.i.i = icmp eq i8* %str10, %str11
   br i1 %cmp.i13.i.i.i, label %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, label %if.end5
 
 _ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit: ; preds = %lor.rhs.i.i.i
   %cmp.i.i.i.i = icmp eq i8* %str8, %str9
   br i1 %cmp.i.i.i.i, label %if.then3, label %if.end5
 
 if.then3:                                         ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %land.rhs.i
   %tmp11 = load i8, i8* %str14, align 8
   %tmp12 = and i8 %tmp11, 2
   %tmp13 = icmp ne i8 %tmp12, 0
   br label %return
 
 if.end5:                                          ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %lor.rhs.i.i.i
 ; CHECK: %if.end5
 ; CHECK: tbz
-  br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i19
+  br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i19, !prof !1
 
 land.rhs.i19:                                     ; preds = %if.end5
   %cmp.i.i.i18 = icmp eq i8* %str6, %str7
   br i1 %cmp.i.i.i18, label %if.then7, label %lor.rhs.i.i.i23
 
 lor.rhs.i.i.i23:                                  ; preds = %land.rhs.i19
   %cmp.i13.i.i.i22 = icmp eq i8* %str3, %str4
   br i1 %cmp.i13.i.i.i22, label %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, label %if.end12
if.end12:                                         ; preds = %if.then7, %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, %lor.rhs.i.i.i23, %if.end5, %if.end
   br label %return
 
 return:                                           ; preds = %if.end12, %if.then9, %if.then3, %entry
   %retval.0 = phi i1 [ %tmp13, %if.then3 ], [ %tmp25, %if.then9 ], [ %lnot, %if.end12 ], [ true, %entry ]
   ret i1 %retval.0
 }
 
 attributes #0 = { nounwind ssp }
+!1 = !{!"branch_weights", i32 3, i32 5}

test/CodeGen/AArch64/compare-branch.ll

 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
 @var32 = global i32 0
 @var64 = global i64 0
 
 define void @foo() {
 ; CHECK-LABEL: foo:
 
   %val1 = load volatile i32, i32* @var32
   %tst1 = icmp eq i32 %val1, 0
-  br i1 %tst1, label %end, label %test2
+  br i1 %tst1, label %end, label %test2, !prof !1
 ; CHECK: cbz {{w[0-9]+}}, .LBB
 
 test2:
   %val2 = load volatile i32, i32* @var32
   %tst2 = icmp ne i32 %val2, 0
-  br i1 %tst2, label %end, label %test3
+  br i1 %tst2, label %end, label %test3, !prof !1
 ; CHECK: cbnz {{w[0-9]+}}, .LBB
 
 test3:
   %val3 = load volatile i64, i64* @var64
   %tst3 = icmp eq i64 %val3, 0
-  br i1 %tst3, label %end, label %test4
+  br i1 %tst3, label %end, label %test4, !prof !1
 ; CHECK: cbz {{x[0-9]+}}, .LBB
 
 test4:
   %val4 = load volatile i64, i64* @var64
   %tst4 = icmp ne i64 %val4, 0
-  br i1 %tst4, label %end, label %test5
+  br i1 %tst4, label %end, label %test5, !prof !1
 ; CHECK: cbnz {{x[0-9]+}}, .LBB
 
 test5:
   store volatile i64 %val4, i64* @var64
   ret void
 
 end:
   ret void
 }
+
+
+!1 = !{!"branch_weights", i32 1, i32 1}

test/CodeGen/AArch64/logical_shifted_reg.ll

 ; CHECK-LABEL: flag_setting:
   %val1 = load i64, i64* @var1_64
   %val2 = load i64, i64* @var2_64
 
 ; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}
 ; CHECK: b.gt .L
   %simple_and = and i64 %val1, %val2
   %tst1 = icmp sgt i64 %simple_and, 0
-  br i1 %tst1, label %ret, label %test2
+  br i1 %tst1, label %ret, label %test2, !prof !1
 
 test2:
 ; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
 ; CHECK: b.lt .L
   %shifted_op = shl i64 %val2, 63
   %shifted_and = and i64 %val1, %shifted_op
   %tst2 = icmp slt i64 %shifted_and, 0
-  br i1 %tst2, label %ret, label %test3
+  br i1 %tst2, label %ret, label %test3, !prof !1
 
 test3:
 ; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, asr #12
 ; CHECK: b.gt .L
   %asr_op = ashr i64 %val2, 12
   %asr_and = and i64 %asr_op, %val1
   %tst3 = icmp sgt i64 %asr_and, 0
-  br i1 %tst3, label %ret, label %other_exit
+  br i1 %tst3, label %ret, label %other_exit, !prof !1
 
 other_exit:
   store volatile i64 %val1, i64* @var1_64
   ret void
 ret:
   ret void
 }
+
+!1 = !{!"branch_weights", i32 1, i32 1}

test/CodeGen/SystemZ/tdc-06.ll

 ; Test the Test Data Class instruction, as used by fpclassify.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ;
 
 declare float @llvm.fabs.f32(float)
 declare double @llvm.fabs.f64(double)
 declare fp128 @llvm.fabs.f128(fp128)
 
 define i32 @fpc(double %x) {
 entry:
 ; CHECK-LABEL: fpc
 ; CHECK: lhi %r2, 5
 ; CHECK: ltdbr %f0, %f0
 ; CHECK: je [[RET:.L.*]]
   %testeq = fcmp oeq double %x, 0.000000e+00
-  br i1 %testeq, label %ret, label %nonzero
+  br i1 %testeq, label %ret, label %nonzero, !prof !1
 
 nonzero:
 ; CHECK: lhi %r2, 1
 ; CHECK: cdbr %f0, %f0
 ; CHECK: jo [[RET]]
   %testnan = fcmp uno double %x, 0.000000e+00
-  br i1 %testnan, label %ret, label %nonzeroord
+  br i1 %testnan, label %ret, label %nonzeroord, !prof !1
 
 nonzeroord:
 ; CHECK: lhi %r2, 2
 ; CHECK: tcdb %f0, 48
 ; CHECK: jl [[RET]]
   %abs = tail call double @llvm.fabs.f64(double %x)
   %testinf = fcmp oeq double %abs, 0x7FF0000000000000
-  br i1 %testinf, label %ret, label %finite
+  br i1 %testinf, label %ret, label %finite, !prof !1
 
 finite:
 ; CHECK: lhi %r2, 3
 ; CHECK: tcdb %f0, 831
 ; CHECK: blr %r14
 ; CHECK: lhi %r2, 4
   %testnormal = fcmp uge double %abs, 0x10000000000000
   %finres = select i1 %testnormal, i32 3, i32 4
   br label %ret
 
 ret:
 ; CHECK: [[RET]]:
 ; CHECK: br %r14
   %res = phi i32 [ 5, %entry ], [ 1, %nonzero ], [ 2, %nonzeroord ], [ %finres, %finite ]
   ret i32 %res
 }
+
+!1 = !{!"branch_weights", i32 1, i32 1}