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Differential D22763

AMDGPU/R600: Remove dead custom inserters
ClosedPublic

Authored by arsenm on Jul 25 2016, 9:33 AM.

Details

Reviewers
• tstellarAMD
Summary

The intrinsics for these were removed, so this is dead.

Diff Detail

Event Timeline

arsenm updated this revision to Diff 65361.Jul 25 2016, 9:33 AM
arsenm retitled this revision from to AMDGPU/R600: Remove dead custom inserters.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: kzhuravl, arsenm. · View Herald TranscriptJul 25 2016, 9:33 AM
• tstellarAMD accepted this revision.Jul 26 2016, 1:24 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Jul 26 2016, 1:24 PM
arsenm closed this revision.Jul 26 2016, 2:11 PM

r276805

Revision Contents

PathSize
lib/
Target/
AMDGPU/
210 lines

Diff 65361

lib/Target/AMDGPU/R600ISelLowering.cpp

Show First 20 Lines • Show All 310 Lines • ▼ Show 20 LinesR600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case AMDGPU::RAT_STORE_TYPED_eg: { case AMDGPU::RAT_STORE_TYPED_eg: {
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode())) BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
.addOperand(MI.getOperand(0)) .addOperand(MI.getOperand(0))
.addOperand(MI.getOperand(1)) .addOperand(MI.getOperand(1))
.addOperand(MI.getOperand(2)) .addOperand(MI.getOperand(2))
.addImm(isEOP(I)); // Set End of program bit .addImm(isEOP(I)); // Set End of program bit
break; break;
} }
case AMDGPU::TXD: {
unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
MachineOperand &RID = MI.getOperand(4);
MachineOperand &SID = MI.getOperand(5);
unsigned TextureId = MI.getOperand(6).getImm();
unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
switch (TextureId) {
case 5: // Rect
CTX = CTY = 0;
break;
case 6: // Shadow1D
SrcW = SrcZ;
break;
case 7: // Shadow2D
SrcW = SrcZ;
break;
case 8: // ShadowRect
CTX = CTY = 0;
SrcW = SrcZ;
break;
case 9: // 1DArray
SrcZ = SrcY;
CTZ = 0;
break;
case 10: // 2DArray
CTZ = 0;
break;
case 11: // Shadow1DArray
SrcZ = SrcY;
CTZ = 0;
break;
case 12: // Shadow2DArray
CTZ = 0;
break;
}
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H),
T0)
.addOperand(MI.getOperand(3))
.addImm(SrcX)
.addImm(SrcY)
.addImm(SrcZ)
.addImm(SrcW)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(1)
.addImm(2)
.addImm(3)
.addOperand(RID)
.addOperand(SID)
.addImm(CTX)
.addImm(CTY)
.addImm(CTZ)
.addImm(CTW);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V),
T1)
.addOperand(MI.getOperand(2))
.addImm(SrcX)
.addImm(SrcY)
.addImm(SrcZ)
.addImm(SrcW)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(1)
.addImm(2)
.addImm(3)
.addOperand(RID)
.addOperand(SID)
.addImm(CTX)
.addImm(CTY)
.addImm(CTZ)
.addImm(CTW);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
.addOperand(MI.getOperand(0))
.addOperand(MI.getOperand(1))
.addImm(SrcX)
.addImm(SrcY)
.addImm(SrcZ)
.addImm(SrcW)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(1)
.addImm(2)
.addImm(3)
.addOperand(RID)
.addOperand(SID)
.addImm(CTX)
.addImm(CTY)
.addImm(CTZ)
.addImm(CTW)
.addReg(T0, RegState::Implicit)
.addReg(T1, RegState::Implicit);
break;
}
case AMDGPU::TXD_SHADOW: {
unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
MachineOperand &RID = MI.getOperand(4);
MachineOperand &SID = MI.getOperand(5);
unsigned TextureId = MI.getOperand(6).getImm();
unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
switch (TextureId) {
case 5: // Rect
CTX = CTY = 0;
break;
case 6: // Shadow1D
SrcW = SrcZ;
break;
case 7: // Shadow2D
SrcW = SrcZ;
break;
case 8: // ShadowRect
CTX = CTY = 0;
SrcW = SrcZ;
break;
case 9: // 1DArray
SrcZ = SrcY;
CTZ = 0;
break;
case 10: // 2DArray
CTZ = 0;
break;
case 11: // Shadow1DArray
SrcZ = SrcY;
CTZ = 0;
break;
case 12: // Shadow2DArray
CTZ = 0;
break;
}
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H),
T0)
.addOperand(MI.getOperand(3))
.addImm(SrcX)
.addImm(SrcY)
.addImm(SrcZ)
.addImm(SrcW)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(1)
.addImm(2)
.addImm(3)
.addOperand(RID)
.addOperand(SID)
.addImm(CTX)
.addImm(CTY)
.addImm(CTZ)
.addImm(CTW);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V),
T1)
.addOperand(MI.getOperand(2))
.addImm(SrcX)
.addImm(SrcY)
.addImm(SrcZ)
.addImm(SrcW)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(1)
.addImm(2)
.addImm(3)
.addOperand(RID)
.addOperand(SID)
.addImm(CTX)
.addImm(CTY)
.addImm(CTZ)
.addImm(CTW);
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
.addOperand(MI.getOperand(0))
.addOperand(MI.getOperand(1))
.addImm(SrcX)
.addImm(SrcY)
.addImm(SrcZ)
.addImm(SrcW)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(0)
.addImm(1)
.addImm(2)
.addImm(3)
.addOperand(RID)
.addOperand(SID)
.addImm(CTX)
.addImm(CTY)
.addImm(CTZ)
.addImm(CTW)
.addReg(T0, RegState::Implicit)
.addReg(T1, RegState::Implicit);
break;
}
case AMDGPU::BRANCH: case AMDGPU::BRANCH:
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP)) BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
.addOperand(MI.getOperand(0)); .addOperand(MI.getOperand(0));
break; break;
case AMDGPU::BRANCH_COND_f32: { case AMDGPU::BRANCH_COND_f32: {
MachineInstr *NewMI = MachineInstr *NewMI =
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X), BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines case AMDGPUIntrinsic::r600_texc: {
switch (IntrinsicID) { switch (IntrinsicID) {
case AMDGPUIntrinsic::r600_tex: case AMDGPUIntrinsic::r600_tex:
TextureOp = 0; TextureOp = 0;
break; break;
case AMDGPUIntrinsic::r600_texc: case AMDGPUIntrinsic::r600_texc:
TextureOp = 1; TextureOp = 1;
break; break;
default: default:
llvm_unreachable("Unknow Texture Operation"); llvm_unreachable("unhandled texture operation");
} }
SDValue TexArgs[19] = { SDValue TexArgs[19] = {
DAG.getConstant(TextureOp, DL, MVT::i32), DAG.getConstant(TextureOp, DL, MVT::i32),
Op.getOperand(1), Op.getOperand(1),
DAG.getConstant(0, DL, MVT::i32), DAG.getConstant(0, DL, MVT::i32),
DAG.getConstant(1, DL, MVT::i32), DAG.getConstant(1, DL, MVT::i32),
DAG.getConstant(2, DL, MVT::i32), DAG.getConstant(2, DL, MVT::i32),
▲ Show 20 Lines • Show All 1,703 Lines • Show Last 20 Lines