AMDGPU: Fix missing test for addressing mode with odd offsets

[arsenm]

Summary

Add test if the constant offset looks unaligned.

[arsenm]

ping

[• tstellarAMD]

LGTM.

[arsenm]

r278589

lib/Target/AMDGPU/SIISelLowering.cpp

if (Subtarget->getGeneration() >= SISubtarget::VOLCANIC_ISLANDS) {
       return isLegalFlatAddressingMode(AM);
     }
 
     return isLegalMUBUFAddressingMode(AM);
   }
   case AMDGPUAS::CONSTANT_ADDRESS: {
     // If the offset isn't a multiple of 4, it probably isn't going to be
     // correctly aligned.
+    // FIXME: Can we get the real alignment here?
     if (AM.BaseOffs % 4 != 0)
       return isLegalMUBUFAddressingMode(AM);
 
     // There are no SMRD extloads, so if we have to do a small type access we
     // will use a MUBUF load.
     // FIXME?: We also need to do this if unaligned, but we don't know the
     // alignment here.
     if (DL.getTypeStoreSize(Ty) < 4)

test/CodeGen/AMDGPU/cgp-addressing-modes.ll

endif:
   %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
   store i32 %x, i32 addrspace(1)* %out.gep
   br label %done
 
 done:
   ret void
 }
 
-attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind }
-
-
-
 ; OPT-LABEL: @test_sink_constant_small_offset_i32
 ; OPT-NOT:  getelementptr i32, i32 addrspace(2)*
 ; OPT: br i1
 
 ; GCN-LABEL: {{^}}test_sink_constant_small_offset_i32:
 ; GCN: s_and_saveexec_b64
 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x7{{$}}
 ; GCN: s_or_b64 exec, exec

 
 bb33:
   unreachable
 
 bb34:
   unreachable
 }
 
+; Address offset is not a multiple of 4. This is a valid mubuf offset,
+; but not smrd.
+
+; OPT-LABEL: @test_sink_constant_small_max_mubuf_offset_load_i32_align_1(
+; OPT: br i1 %tmp0,
+; OPT: if:
+; OPT: %sunkaddr = ptrtoint i8 addrspace(2)* %in to i64
+; OPT: %sunkaddr1 = add i64 %sunkaddr, 4095
+define void @test_sink_constant_small_max_mubuf_offset_load_i32_align_1(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
+entry:
+  %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024
+  %in.gep = getelementptr i8, i8 addrspace(2)* %in, i64 4095
+  %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
+  %tmp0 = icmp eq i32 %tid, 0
+  br i1 %tmp0, label %endif, label %if
+
+if:
+  %bitcast = bitcast i8 addrspace(2)* %in.gep to i32 addrspace(2)*
+  %tmp1 = load i32, i32 addrspace(2)* %bitcast, align 1
+  br label %endif
+
+endif:
+  %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
+  store i32 %x, i32 addrspace(1)* %out.gep
+  br label %done
+
+done:
+  ret void
+}
+
 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
 
 attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }