AMDGPU: Don't reinvent transferSuccessorsAndUpdatePHIs

[• tstellarAMD]

LGTM.

[arsenm]

r276434

lib/Target/AMDGPU/SIISelLowering.cpp

unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
   default:
     llvm_unreachable("missing register type checking");
   }
 
   report_fatal_error(Twine("invalid type for register \""
                            + StringRef(RegName) + "\"."));
 }
 
-static void replaceSuccessorPhisWith(MachineBasicBlock &BB,
-                                     MachineBasicBlock &SplitBB) {
-  for (MachineBasicBlock *Succ : BB.successors()) {
-    for (MachineInstr &MI : *Succ) {
-      if (!MI.isPHI())
-        break;
-
-      for (unsigned I = 2, E = MI.getNumOperands(); I != E; I += 2) {
-        MachineOperand &FromBB = MI.getOperand(I);
-        if (&BB == FromBB.getMBB()) {
-          FromBB.setMBB(&SplitBB);
-          break;
-        }
-      }
-    }
-  }
-}
-
 // If kill is not the last instruction, split the block so kill is always a
 // proper terminator.
 MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
                                                     MachineBasicBlock *BB) const {
   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
 
   MachineBasicBlock::iterator SplitPoint(&MI);
   ++SplitPoint;
 
   if (SplitPoint == BB->end()) {
     // Don't bother with a new block.
     MI.setDesc(TII->get(AMDGPU::SI_KILL_TERMINATOR));
     return BB;
   }
 
   MachineFunction *MF = BB->getParent();
   MachineBasicBlock *SplitBB
     = MF->CreateMachineBasicBlock(BB->getBasicBlock());
 
-  // Fix the block phi references to point to the new block for the defs in the
-  // second piece of the block.
-  replaceSuccessorPhisWith(*BB, *SplitBB);
-
   MF->insert(++MachineFunction::iterator(BB), SplitBB);
   SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
 
-  SplitBB->transferSuccessors(BB);
+  SplitBB->transferSuccessorsAndUpdatePHIs(BB);
   BB->addSuccessor(SplitBB);
 
   MI.setDesc(TII->get(AMDGPU::SI_KILL_TERMINATOR));
   return SplitBB;
 }
 
 // Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
 // wavefront. If the value is uniform and just happens to be in a VGPR, this
static MachineBasicBlock *loadM0FromVGPR(const SIInstrInfo *TII,
   MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
   MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
   MachineFunction::iterator MBBI(MBB);
   ++MBBI;
 
   MF->insert(MBBI, LoopBB);
   MF->insert(MBBI, RemainderBB);
 
-  replaceSuccessorPhisWith(MBB, *RemainderBB);
-
   LoopBB->addSuccessor(LoopBB);
   LoopBB->addSuccessor(RemainderBB);
 
   // Move the rest of the block into a new block.
-  RemainderBB->transferSuccessors(&MBB);
+  RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
   RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
 
   MBB.addSuccessor(LoopBB);
 
   const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
 
   emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, MovRel, *Idx,
                          InitResultReg, DstReg, PhiReg, TmpExec, Offset);