[NVPTX] deal with all aggregate return types.

[tra]

Summary

Fixes a crash in llvm_unreachable when a function has array return type.

[tra]

renamed vector-return.ll -> aggregate-return.ll and added tests for array and structure return types.

[jlebar]

test/CodeGen/NVPTX/aggregate-return.ll

10

Do we need this line? Same below.

[tra]

Removed unneeded entry label and fixed names of patterns in the last test.

lib/Target/NVPTX/NVPTXAsmPrinter.cpp

if (Ty->isFloatingPointTy() || Ty->isIntegerTy()) {
         assert(Ty->isFloatingPointTy() && "Floating point type expected here");
         size = Ty->getPrimitiveSizeInBits();
       }
 
       O << ".param .b" << size << " func_retval0";
     } else if (isa<PointerType>(Ty)) {
       O << ".param .b" << TLI->getPointerTy(DL).getSizeInBits()
         << " func_retval0";
-    } else if ((Ty->getTypeID() == Type::StructTyID) || isa<VectorType>(Ty)) {
+    } else if (Ty->isAggregateType() || Ty->isVectorTy()) {
       unsigned totalsz = DL.getTypeAllocSize(Ty);
-       unsigned retAlignment = 0;
-       if (!llvm::getAlign(*F, 0, retAlignment))
-         retAlignment = DL.getABITypeAlignment(Ty);
-       O << ".param .align " << retAlignment << " .b8 func_retval0[" << totalsz
-         << "]";
     } else
       llvm_unreachable("Unknown return type");
   } else {
     SmallVector<EVT, 16> vtparts;
     ComputeValueVTs(*TLI, DL, Ty, vtparts);
     unsigned idx = 0;
     for (unsigned i = 0, e = vtparts.size(); i != e; ++i) {
       unsigned elems = 1;

test/CodeGen/NVPTX/aggregate-return.ll

+; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
+
+declare <2 x float> @barv(<2 x float> %input)
+declare [2 x float] @bara([2 x float] %input)
+declare {float, float} @bars({float, float} %input)
+
+define void @foov(<2 x float> %input, <2 x float>* %output) {
+; CHECK-LABEL: @foov
+  %call = tail call <2 x float> @barv(<2 x float> %input)
+; CHECK: .param .align 8 .b8 retval0[8];
+; CHECK: ld.param.v2.f32 {[[ELEMV1:%f[0-9]+]], [[ELEMV2:%f[0-9]+]]}, [retval0+0];
+  store <2 x float> %call, <2 x float>* %output, align 8
+; CHECK: st.v2.f32 [{{%rd[0-9]+}}], {[[ELEMV1]], [[ELEMV2]]}
+  ret void
+}
+
+define void @fooa([2 x float] %input, [2 x float]* %output) {
+; CHECK-LABEL: @fooa
+  %call = tail call [2 x float] @bara([2 x float] %input)
+; CHECK: .param .align 4 .b8 retval0[8];
+; CHECK-DAG: ld.param.f32 [[ELEMA1:%f[0-9]+]], [retval0+0];
+; CHECK-DAG: ld.param.f32 [[ELEMA2:%f[0-9]+]], [retval0+4];
+  store [2 x float] %call, [2 x float]* %output, align 4
+; CHECK: }
+; CHECK-DAG: st.f32 [{{%rd[0-9]+}}], [[ELEMA1]]
+; CHECK-DAG: st.f32 [{{%rd[0-9]+}}+4], [[ELEMA2]]
+  ret void
+; CHECK: ret
+}
+
+define void @foos({float, float} %input, {float, float}* %output) {
+; CHECK-LABEL: @foos
+  %call = tail call {float, float} @bars({float, float} %input)
+; CHECK: .param .align 4 .b8 retval0[8];
+; CHECK-DAG: ld.param.f32 [[ELEMS1:%f[0-9]+]], [retval0+0];
+; CHECK-DAG: ld.param.f32 [[ELEMS2:%f[0-9]+]], [retval0+4];
+  store {float, float} %call, {float, float}* %output, align 4
+; CHECK: }
+; CHECK-DAG: st.f32 [{{%rd[0-9]+}}], [[ELEMS1]]
+; CHECK-DAG: st.f32 [{{%rd[0-9]+}}+4], [[ELEMS2]]
+  ret void
+; CHECK: ret
+}

test/CodeGen/NVPTX/vector-return.ll

-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
-
-declare <2 x float> @bar(<2 x float> %input)
-
-define void @foo(<2 x float> %input, <2 x float>* %output) {
-; CHECK-LABEL: @foo
-entry:
-  %call = tail call <2 x float> @bar(<2 x float> %input)
-; CHECK: .param .align 8 .b8 retval0[8];
-; CHECK: ld.param.v2.f32 {[[ELEM1:%f[0-9]+]], [[ELEM2:%f[0-9]+]]}, [retval0+0];
-  store <2 x float> %call, <2 x float>* %output, align 8
-; CHECK: st.v2.f32 [{{%rd[0-9]+}}], {[[ELEM1]], [[ELEM2]]}
-  ret void
-}