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Differential D22412

[mips] Correct label prefixes for N32 and N64.
ClosedPublic

Authored by dsanders on Jul 15 2016, 9:10 AM.

Details

Reviewers
sdardis
Commits
rG3ce6eededa8b: Merging Clang-side of r275967: (the LLVM side already merged in r276561)…
rG120ca53c91d4: Merging r275967: --------------------------------------------------------------…
rG6a73883c48fb: [mips] Correct label prefixes for N32 and N64.
rC275967: [mips] Correct label prefixes for N32 and N64.
rL275967: [mips] Correct label prefixes for N32 and N64.
Summary

N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own
($).

This fixes the majority of object differences between -fintegrated-as and
-fno-integrated-as.

The DataLayout change will need a trivial corresponding change in clang. This
will be committed along with this patch.

Diff Detail

Repository
rL LLVM

Event Timeline

dsanders updated this revision to Diff 64146.Jul 15 2016, 9:10 AM
dsanders retitled this revision from to [mips] Correct label prefixes for N32 and N64..
dsanders updated this object.
dsanders added a reviewer: sdardis.
dsanders added a subscriber: llvm-commits.
Herald added subscribers: sdardis, dsanders. · View Herald TranscriptJul 15 2016, 9:10 AM
sdardis accepted this revision.Jul 19 2016, 2:04 AM
sdardis edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Jul 19 2016, 2:04 AM
Closed by commit rL275967: [mips] Correct label prefixes for N32 and N64. (authored by dsanders). · Explain WhyJul 19 2016, 3:56 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
cfe/
trunk/
lib/
Basic/
4 lines
test/
CodeGen/
8 lines
llvm/
trunk/
lib/
Target/
Mips/
MCTargetDesc/
11 lines
5 lines
test/
CodeGen/
Mips/
16 lines
6 lines
6 lines
138 lines
4 lines
32 lines
12 lines
16 lines
30 lines
75 lines
llvm-ir/
8 lines
4 lines
8 lines
38 lines
40 lines
27 lines
8 lines
14 lines
msa/
40 lines
36 lines
16 lines
MC/
Mips/
16 lines
14 lines
20 lines
mips3/
4 lines
mips4/
4 lines
mips5/
4 lines
mips64/
4 lines
mips64r2/
4 lines
mips64r3/
4 lines
mips64r5/
4 lines

Diff 64465

cfe/trunk/lib/Basic/Targets.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,099 Lines • ▼ Show 20 Lines
class MipsTargetInfo : public TargetInfo { class MipsTargetInfo : public TargetInfo {
void setDataLayout() { void setDataLayout() {
StringRef Layout; StringRef Layout;
if (ABI == "o32") if (ABI == "o32")
Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
else if (ABI == "n32") else if (ABI == "n32")
Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
else if (ABI == "n64") else if (ABI == "n64")
Layout = "m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
else else
llvm_unreachable("Invalid ABI"); llvm_unreachable("Invalid ABI");
if (BigEndian) if (BigEndian)
resetDataLayout(("E-" + Layout).str()); resetDataLayout(("E-" + Layout).str());
else else
resetDataLayout(("e-" + Layout).str()); resetDataLayout(("e-" + Layout).str());
} }
▲ Show 20 Lines • Show All 1,498 Lines • Show Last 20 Lines

cfe/trunk/test/CodeGen/target-data.c

Show All 34 Lines
// MIPS-32EL: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" // MIPS-32EL: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
// RUN: %clang_cc1 -triple mips-linux-gnu -o - -emit-llvm %s | \ // RUN: %clang_cc1 -triple mips-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-32EB // RUN: FileCheck %s -check-prefix=MIPS-32EB
// MIPS-32EB: target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" // MIPS-32EB: target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
// RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm %s | \ // RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EL // RUN: FileCheck %s -check-prefix=MIPS-64EL
// MIPS-64EL: target datalayout = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128" // MIPS-64EL: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
// RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm -target-abi n32 \ // RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm -target-abi n32 \
// RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32 // RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
// MIPS-64EL-N32: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128" // MIPS-64EL-N32: target datalayout = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
// RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s | \ // RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=MIPS-64EB // RUN: FileCheck %s -check-prefix=MIPS-64EB
// MIPS-64EB: target datalayout = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128" // MIPS-64EB: target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
// RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s -target-abi n32 \ // RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s -target-abi n32 \
// RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32 // RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
// MIPS-64EB-N32: target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128" // MIPS-64EB-N32: target datalayout = "E-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
// RUN: %clang_cc1 -triple powerpc64-lv2 -o - -emit-llvm %s | \ // RUN: %clang_cc1 -triple powerpc64-lv2 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=PS3 // RUN: FileCheck %s -check-prefix=PS3
// PS3: target datalayout = "E-m:e-p:32:32-i64:64-n32:64" // PS3: target datalayout = "E-m:e-p:32:32-i64:64-n32:64"
// RUN: %clang_cc1 -triple i686-nacl -o - -emit-llvm %s | \ // RUN: %clang_cc1 -triple i686-nacl -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=I686-NACL // RUN: FileCheck %s -check-prefix=I686-NACL
// I686-NACL: target datalayout = "e-m:e-p:32:32-i64:64-n8:16:32-S128" // I686-NACL: target datalayout = "e-m:e-p:32:32-i64:64-n8:16:32-S128"
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llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp

Show All 22 Lines if ((TheTriple.getArch() == Triple::mips) ||
(TheTriple.getArch() == Triple::mips64)) (TheTriple.getArch() == Triple::mips64))
IsLittleEndian = false; IsLittleEndian = false;
if ((TheTriple.getArch() == Triple::mips64el) || if ((TheTriple.getArch() == Triple::mips64el) ||
(TheTriple.getArch() == Triple::mips64)) { (TheTriple.getArch() == Triple::mips64)) {
PointerSize = CalleeSaveStackSlotSize = 8; PointerSize = CalleeSaveStackSlotSize = 8;
} }
// FIXME: This condition isn't quite right but it's the best we can do until
// this object can identify the ABI. It will misbehave when using O32
// on a mips64*-* triple.
if ((TheTriple.getArch() == Triple::mipsel) ||
(TheTriple.getArch() == Triple::mips)) {
PrivateGlobalPrefix = "$";
PrivateLabelPrefix = "$";
}
AlignmentIsInBytes = false; AlignmentIsInBytes = false;
Data16bitsDirective = "\t.2byte\t"; Data16bitsDirective = "\t.2byte\t";
Data32bitsDirective = "\t.4byte\t"; Data32bitsDirective = "\t.4byte\t";
Data64bitsDirective = "\t.8byte\t"; Data64bitsDirective = "\t.8byte\t";
PrivateGlobalPrefix = "$";
PrivateLabelPrefix = "$";
CommentString = "#"; CommentString = "#";
ZeroDirective = "\t.space\t"; ZeroDirective = "\t.space\t";
GPRel32Directive = "\t.gpword\t"; GPRel32Directive = "\t.gpword\t";
GPRel64Directive = "\t.gpdword\t"; GPRel64Directive = "\t.gpdword\t";
UseAssignmentForEHBegin = true; UseAssignmentForEHBegin = true;
SupportsDebugInformation = true; SupportsDebugInformation = true;
ExceptionsType = ExceptionHandling::DwarfCFI; ExceptionsType = ExceptionHandling::DwarfCFI;
DwarfRegNumForCFI = true; DwarfRegNumForCFI = true;
// Enable IAS by default for O32. // Enable IAS by default for O32.
if (TheTriple.getArch() == Triple::mips || if (TheTriple.getArch() == Triple::mips ||
TheTriple.getArch() == Triple::mipsel) TheTriple.getArch() == Triple::mipsel)
UseIntegratedAssembler = true; UseIntegratedAssembler = true;
} }

llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Linesstatic std::string computeDataLayout(const Triple &TT, StringRef CPU,
MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
// There are both little and big endian mips. // There are both little and big endian mips.
if (isLittle) if (isLittle)
Ret += "e"; Ret += "e";
else else
Ret += "E"; Ret += "E";
if (ABI.IsO32())
Ret += "-m:m"; Ret += "-m:m";
else
Ret += "-m:e";
// Pointers are 32 bit on some ABIs. // Pointers are 32 bit on some ABIs.
if (!ABI.IsN64()) if (!ABI.IsN64())
Ret += "-p:32:32"; Ret += "-p:32:32";
// 8 and 16 bit integers only need to have natural alignment, but try to // 8 and 16 bit integers only need to have natural alignment, but try to
// align them to 32 bits. 64 bit integers have natural alignment. // align them to 32 bits. 64 bit integers have natural alignment.
Ret += "-i8:8:32-i16:16:32-i64:64"; Ret += "-i8:8:32-i16:16:32-i64:64";
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llvm/trunk/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll

; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32 ; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32
; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-O32 ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-O32
; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32
; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
define float @h() nounwind readnone { define float @h() nounwind readnone {
entry: entry:
; PIC-O32: lw $[[R0:[0-9]+]], %got($CPI0_0) ; PIC-O32: lw $[[R0:[0-9]+]], %got($CPI0_0)
; PIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]]) ; PIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]])
; STATIC-O32: lui $[[R0:[0-9]+]], %hi($CPI0_0) ; STATIC-O32: lui $[[R0:[0-9]+]], %hi($CPI0_0)
; STATIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]]) ; STATIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]])
; PIC-N32: lw $[[R0:[0-9]+]], %got_page($CPI0_0) ; PIC-N32: lw $[[R0:[0-9]+]], %got_page(.LCPI0_0)
; PIC-N32: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]]) ; PIC-N32: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]])
; STATIC-N32: lui $[[R0:[0-9]+]], %hi($CPI0_0) ; STATIC-N32: lui $[[R0:[0-9]+]], %hi(.LCPI0_0)
; STATIC-N32: lwc1 $f0, %lo($CPI0_0)($[[R0]]) ; STATIC-N32: lwc1 $f0, %lo(.LCPI0_0)($[[R0]])
; PIC-N64: ld $[[R0:[0-9]+]], %got_page($CPI0_0) ; PIC-N64: ld $[[R0:[0-9]+]], %got_page(.LCPI0_0)
; PIC-N64: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]]) ; PIC-N64: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]])
; STATIC-N64: ld $[[R0:[0-9]+]], %got_page($CPI0_0) ; STATIC-N64: ld $[[R0:[0-9]+]], %got_page(.LCPI0_0)
; STATIC-N64: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]]) ; STATIC-N64: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]])
ret float 0x400B333340000000 ret float 0x400B333340000000
} }

llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll

Show All 21 Lines
; STATIC-O32: lw $[[R3:[0-9]+]], %lo($JTI0_0)($[[R2]]) ; STATIC-O32: lw $[[R3:[0-9]+]], %lo($JTI0_0)($[[R2]])
; PIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2 ; PIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
; PIC-O32: lw $[[R1:[0-9]+]], %got($JTI0_0) ; PIC-O32: lw $[[R1:[0-9]+]], %got($JTI0_0)
; PIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; PIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]]) ; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]])
; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]] ; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
; PIC-O32: jr $[[R5]] ; PIC-O32: jr $[[R5]]
; N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3 ; N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3
; N64: ld $[[R1:[0-9]+]], %got_page($JTI0_0) ; N64: ld $[[R1:[0-9]+]], %got_page(.LJTI0_0)
; N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]] ; N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]]
; N64: ld $[[R4:[0-9]+]], %got_ofst($JTI0_0)($[[R2]]) ; N64: ld $[[R4:[0-9]+]], %got_ofst(.LJTI0_0)($[[R2]])
; N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]] ; N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
; N64: jr $[[R5]] ; N64: jr $[[R5]]
switch i32 %0, label %bb4 [ switch i32 %0, label %bb4 [
i32 0, label %bb5 i32 0, label %bb5
i32 1, label %bb1 i32 1, label %bb1
i32 2, label %bb2 i32 2, label %bb2
i32 3, label %bb3 i32 3, label %bb3
] ]
Show All 22 Lines
; STATIC-O32: .4byte ; STATIC-O32: .4byte
; PIC-O32: .p2align 2 ; PIC-O32: .p2align 2
; PIC-O32: $JTI0_0: ; PIC-O32: $JTI0_0:
; PIC-O32: .gpword ; PIC-O32: .gpword
; PIC-O32: .gpword ; PIC-O32: .gpword
; PIC-O32: .gpword ; PIC-O32: .gpword
; PIC-O32: .gpword ; PIC-O32: .gpword
; N64: .p2align 3 ; N64: .p2align 3
; N64: $JTI0_0: ; N64: .LJTI0_0:
; N64: .gpdword ; N64: .gpdword
; N64: .gpdword ; N64: .gpdword
; N64: .gpdword ; N64: .gpdword
; N64: .gpdword ; N64: .gpdword

llvm/trunk/test/CodeGen/Mips/analyzebranch.ll

; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,FCC ; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,FCC
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,FCC ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,FCC
; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,32-GPR ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,FCC ; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,FCC
; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,FCC ; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,FCC
; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,FCC ; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,FCC
; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,64-GPR ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
define double @foo(double %a, double %b) nounwind readnone { define double @foo(double %a, double %b) nounwind readnone {
entry: entry:
; ALL-LABEL: foo: ; ALL-LABEL: foo:
; FCC: bc1f $BB ; FCC: bc1f {{\$|\.L}}BB
; FCC: nop ; FCC: nop
; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]] ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]] ; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]] ; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12 ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; GPR: bnezc $[[GPRCC]], $BB ; GPR: bnezc $[[GPRCC]], {{\$|\.L}}BB
%cmp = fcmp ogt double %a, 0.000000e+00 %cmp = fcmp ogt double %a, 0.000000e+00
br i1 %cmp, label %if.end6, label %if.else br i1 %cmp, label %if.end6, label %if.else
if.else: ; preds = %entry if.else: ; preds = %entry
%cmp3 = fcmp ogt double %b, 0.000000e+00 %cmp3 = fcmp ogt double %b, 0.000000e+00
br i1 %cmp3, label %if.end6, label %return br i1 %cmp3, label %if.end6, label %return
if.end6: ; preds = %if.else, %entry if.end6: ; preds = %if.else, %entry
%c.0 = phi double [ %a, %entry ], [ 0.000000e+00, %if.else ] %c.0 = phi double [ %a, %entry ], [ 0.000000e+00, %if.else ]
%sub = fsub double %b, %c.0 %sub = fsub double %b, %c.0
%mul = fmul double %sub, 2.000000e+00 %mul = fmul double %sub, 2.000000e+00
br label %return br label %return
return: ; preds = %if.else, %if.end6 return: ; preds = %if.else, %if.end6
%retval.0 = phi double [ %mul, %if.end6 ], [ 0.000000e+00, %if.else ] %retval.0 = phi double [ %mul, %if.end6 ], [ 0.000000e+00, %if.else ]
ret double %retval.0 ret double %retval.0
} }
define void @f1(float %f) nounwind { define void @f1(float %f) nounwind {
entry: entry:
; ALL-LABEL: f1: ; ALL-LABEL: f1:
; FCC: bc1f $BB ; FCC: bc1f {{\$|\.L}}BB
; FCC: nop ; FCC: nop
; GPR: mtc1 $zero, $[[Z:f[0-9]]] ; GPR: mtc1 $zero, $[[Z:f[0-9]]]
; GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $[[Z]] ; GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $[[Z]]
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; 64-GPR beqzc $[[GPRCC]], $BB ; 64-GPR beqzc $[[GPRCC]], $BB
; 32-GPR beqz $[[GPRCC]], $BB ; 32-GPR beqz $[[GPRCC]], $BB
Show All 16 Lines

llvm/trunk/test/CodeGen/Mips/atomic.ll

Show All 28 Linesentry:
%0 = atomicrmw add i32* @x, i32 %incr monotonic %0 = atomicrmw add i32* @x, i32 %incr monotonic
ret i32 %0 ret i32 %0
; ALL-LABEL: AtomicLoadAdd32: ; ALL-LABEL: AtomicLoadAdd32:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
; O0: $[[BB0:[A-Z_0-9]+]]: ; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; O0: ld $[[R1:[0-9]+]] ; O0: ld $[[R1:[0-9]+]]
; O0-NEXT: ll $[[R2:[0-9]+]], 0($[[R1]]) ; O0-NEXT: ll $[[R2:[0-9]+]], 0($[[R1]])
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R3:[0-9]+]], 0($[[R0]]) ; ALL: ll $[[R3:[0-9]+]], 0($[[R0]])
; ALL: addu $[[R4:[0-9]+]], $[[R3]], $4 ; ALL: addu $[[R4:[0-9]+]], $[[R3]], $4
; ALL: sc $[[R4]], 0($[[R0]]) ; ALL: sc $[[R4]], 0($[[R0]])
; NOT-MICROMIPS: beqz $[[R4]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R4]], [[BB0]]
; MICROMIPS: beqzc $[[R4]], $[[BB0]] ; MICROMIPS: beqzc $[[R4]], [[BB0]]
; MIPSR6: beqzc $[[R4]], $[[BB0]] ; MIPSR6: beqzc $[[R4]], [[BB0]]
} }
define i32 @AtomicLoadNand32(i32 signext %incr) nounwind { define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
entry: entry:
%0 = atomicrmw nand i32* @x, i32 %incr monotonic %0 = atomicrmw nand i32* @x, i32 %incr monotonic
ret i32 %0 ret i32 %0
; ALL-LABEL: AtomicLoadNand32: ; ALL-LABEL: AtomicLoadNand32:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) ; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
; ALL: and $[[R3:[0-9]+]], $[[R1]], $4 ; ALL: and $[[R3:[0-9]+]], $[[R1]], $4
; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]] ; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]]
; ALL: sc $[[R2]], 0($[[R0]]) ; ALL: sc $[[R2]], 0($[[R0]])
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R2]], [[BB0]]
; MICROMIPS: beqzc $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], [[BB0]]
; MIPSR6: beqzc $[[R2]], $[[BB0]] ; MIPSR6: beqzc $[[R2]], [[BB0]]
} }
define i32 @AtomicSwap32(i32 signext %newval) nounwind { define i32 @AtomicSwap32(i32 signext %newval) nounwind {
entry: entry:
%newval.addr = alloca i32, align 4 %newval.addr = alloca i32, align 4
store i32 %newval, i32* %newval.addr, align 4 store i32 %newval, i32* %newval.addr, align 4
%tmp = load i32, i32* %newval.addr, align 4 %tmp = load i32, i32* %newval.addr, align 4
%0 = atomicrmw xchg i32* @x, i32 %tmp monotonic %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
ret i32 %0 ret i32 %0
; ALL-LABEL: AtomicSwap32: ; ALL-LABEL: AtomicSwap32:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll ${{[0-9]+}}, 0($[[R0]]) ; ALL: ll ${{[0-9]+}}, 0($[[R0]])
; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R2]], [[BB0]]
; MICROMIPS: beqzc $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], [[BB0]]
; MIPSR6: beqzc $[[R2]], $[[BB0]] ; MIPSR6: beqzc $[[R2]], [[BB0]]
} }
define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind { define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
entry: entry:
%newval.addr = alloca i32, align 4 %newval.addr = alloca i32, align 4
store i32 %newval, i32* %newval.addr, align 4 store i32 %newval, i32* %newval.addr, align 4
%tmp = load i32, i32* %newval.addr, align 4 %tmp = load i32, i32* %newval.addr, align 4
%0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic monotonic %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic monotonic
%1 = extractvalue { i32, i1 } %0, 0 %1 = extractvalue { i32, i1 } %0, 0
ret i32 %1 ret i32 %1
; ALL-LABEL: AtomicCmpSwap32: ; ALL-LABEL: AtomicCmpSwap32:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $2, 0($[[R0]]) ; ALL: ll $2, 0($[[R0]])
; NOT-MICROMIPS: bne $2, $4, $[[BB1:[A-Z_0-9]+]] ; NOT-MICROMIPS: bne $2, $4, [[BB1:(\$|\.L)[A-Z_0-9]+]]
; MICROMIPS: bne $2, $4, $[[BB1:[A-Z_0-9]+]] ; MICROMIPS: bne $2, $4, [[BB1:(\$|\.L)[A-Z_0-9]+]]
; MIPSR6: bnec $2, $4, $[[BB1:[A-Z_0-9]+]] ; MIPSR6: bnec $2, $4, [[BB1:(\$|\.L)[A-Z_0-9]+]]
; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R2]], [[BB0]]
; MICROMIPS: beqzc $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], [[BB0]]
; MIPSR6: beqzc $[[R2]], $[[BB0]] ; MIPSR6: beqzc $[[R2]], [[BB0]]
; ALL: $[[BB1]]: ; ALL: [[BB1]]:
} }
@y = common global i8 0, align 1 @y = common global i8 0, align 1
define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
entry: entry:
Show All 11 Lines
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
; ALL: ori $[[R6:[0-9]+]], $zero, 255 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; O0: $[[BB0:[A-Z_0-9]+]]: ; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; O0: ld $[[R10:[0-9]+]] ; O0: ld $[[R10:[0-9]+]]
; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]] ; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
; ALL: sc $[[R16]], 0($[[R2]]) ; ALL: sc $[[R16]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R16]], [[BB0]]
; MICROMIPS: beqzc $[[R16]], $[[BB0]] ; MICROMIPS: beqzc $[[R16]], [[BB0]]
; MIPSR6: beqzc $[[R16]], $[[BB0]] ; MIPSR6: beqzc $[[R16]], [[BB0]]
; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24 ; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
; NO-SEB-SEH: sra $2, $[[R19]], 24 ; NO-SEB-SEH: sra $2, $[[R19]], 24
; HAS-SEB-SEH: seb $2, $[[R18]] ; HAS-SEB-SEH: seb $2, $[[R18]]
Show All 15 Lines
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
; ALL: ori $[[R6:[0-9]+]], $zero, 255 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; O0: $[[BB0:[A-Z_0-9]+]]: ; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; O0: ld $[[R10:[0-9]+]] ; O0: ld $[[R10:[0-9]+]]
; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]] ; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
; ALL: sc $[[R16]], 0($[[R2]]) ; ALL: sc $[[R16]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R16]], [[BB0]]
; MICROMIPS: beqzc $[[R16]], $[[BB0]] ; MICROMIPS: beqzc $[[R16]], [[BB0]]
; MIPSR6: beqzc $[[R16]], $[[BB0]] ; MIPSR6: beqzc $[[R16]], [[BB0]]
; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24 ; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
; NO-SEB-SEH: sra $2, $[[R19]], 24 ; NO-SEB-SEH: sra $2, $[[R19]], 24
; HAS-SEB-SEH:seb $2, $[[R18]] ; HAS-SEB-SEH:seb $2, $[[R18]]
Show All 15 Lines
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
; ALL: ori $[[R6:[0-9]+]], $zero, 255 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; O0: $[[BB0:[A-Z_0-9]+]]: ; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; O0: ld $[[R10:[0-9]+]] ; O0: ld $[[R10:[0-9]+]]
; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]] ; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]]
; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]] ; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]]
; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]] ; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]]
; ALL: and $[[R16:[0-9]+]], $[[R12]], $[[R8]] ; ALL: and $[[R16:[0-9]+]], $[[R12]], $[[R8]]
; ALL: or $[[R17:[0-9]+]], $[[R16]], $[[R15]] ; ALL: or $[[R17:[0-9]+]], $[[R16]], $[[R15]]
; ALL: sc $[[R17]], 0($[[R2]]) ; ALL: sc $[[R17]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R17]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R17]], [[BB0]]
; MICROMIPS: beqzc $[[R17]], $[[BB0]] ; MICROMIPS: beqzc $[[R17]], [[BB0]]
; MIPSR6: beqzc $[[R17]], $[[BB0]] ; MIPSR6: beqzc $[[R17]], [[BB0]]
; ALL: and $[[R18:[0-9]+]], $[[R12]], $[[R7]] ; ALL: and $[[R18:[0-9]+]], $[[R12]], $[[R7]]
; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]] ; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]]
; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24
; NO-SEB-SEH: sra $2, $[[R20]], 24 ; NO-SEB-SEH: sra $2, $[[R20]], 24
; HAS-SEB-SEH: seb $2, $[[R19]] ; HAS-SEB-SEH: seb $2, $[[R19]]
Show All 15 Lines
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
; ALL: ori $[[R6:[0-9]+]], $zero, 255 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]] ; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
; ALL: sc $[[R14]], 0($[[R2]]) ; ALL: sc $[[R14]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R14]], [[BB0]]
; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; MICROMIPS: beqzc $[[R14]], [[BB0]]
; MIPSR6: beqzc $[[R14]], $[[BB0]] ; MIPSR6: beqzc $[[R14]], [[BB0]]
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 ; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
; NO-SEB-SEH: sra $2, $[[R17]], 24 ; NO-SEB-SEH: sra $2, $[[R17]], 24
; HAS-SEB-SEH: seb $2, $[[R16]] ; HAS-SEB-SEH: seb $2, $[[R16]]
Show All 20 Lines
; ALL: ori $[[R6:[0-9]+]], $zero, 255 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: andi $[[R9:[0-9]+]], $4, 255 ; ALL: andi $[[R9:[0-9]+]], $4, 255
; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]] ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
; ALL: andi $[[R11:[0-9]+]], $5, 255 ; ALL: andi $[[R11:[0-9]+]], $5, 255
; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]] ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
; NOT-MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; NOT-MICROMIPS: bne $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]]
; MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; MICROMIPS: bne $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]]
; MIPSR6: bnec $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; MIPSR6: bnec $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]]
; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
; ALL: sc $[[R16]], 0($[[R2]]) ; ALL: sc $[[R16]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R16]], [[BB0]]
; MICROMIPS: beqzc $[[R16]], $[[BB0]] ; MICROMIPS: beqzc $[[R16]], [[BB0]]
; MIPSR6: beqzc $[[R16]], $[[BB0]] ; MIPSR6: beqzc $[[R16]], [[BB0]]
; ALL: $[[BB1]]: ; ALL: [[BB1]]:
; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24
; NO-SEB-SEH: sra $2, $[[R18]], 24 ; NO-SEB-SEH: sra $2, $[[R18]], 24
; HAS-SEB-SEH: seb $2, $[[R17]] ; HAS-SEB-SEH: seb $2, $[[R17]]
} }
Show All 13 Lines
; ALL: ori $[[R6:[0-9]+]], $zero, 255 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: andi $[[R9:[0-9]+]], $5, 255 ; ALL: andi $[[R9:[0-9]+]], $5, 255
; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]] ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
; ALL: andi $[[R11:[0-9]+]], $6, 255 ; ALL: andi $[[R11:[0-9]+]], $6, 255
; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]] ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
; NOT-MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; NOT-MICROMIPS: bne $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]]
; MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; MICROMIPS: bne $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]]
; MIPSR6: bnec $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; MIPSR6: bnec $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]]
; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
; ALL: sc $[[R16]], 0($[[R2]]) ; ALL: sc $[[R16]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R16]], [[BB0]]
; MICROMIPS: beqzc $[[R16]], $[[BB0]] ; MICROMIPS: beqzc $[[R16]], [[BB0]]
; MIPSR6: beqzc $[[R16]], $[[BB0]] ; MIPSR6: beqzc $[[R16]], [[BB0]]
; ALL: $[[BB1]]: ; ALL: [[BB1]]:
; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24
; NO-SEB-SEH: sra $[[R19:[0-9]+]], $[[R18]], 24 ; NO-SEB-SEH: sra $[[R19:[0-9]+]], $[[R18]], 24
; FIXME: -march=mips produces a redundant sign extension here... ; FIXME: -march=mips produces a redundant sign extension here...
; NO-SEB-SEH: sll $[[R20:[0-9]+]], $5, 24 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $5, 24
; NO-SEB-SEH: sra $[[R20]], $[[R20]], 24 ; NO-SEB-SEH: sra $[[R20]], $[[R20]], 24
Show All 26 Lines
; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 2 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 2
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
; ALL: ori $[[R6:[0-9]+]], $zero, 65535 ; ALL: ori $[[R6:[0-9]+]], $zero, 65535
; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; O0: $[[BB0:[A-Z_0-9]+]]: ; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; O0: ld $[[R10:[0-9]+]] ; O0: ld $[[R10:[0-9]+]]
; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]] ; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
; ALL: sc $[[R16]], 0($[[R2]]) ; ALL: sc $[[R16]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R16]], [[BB0]]
; MICROMIPS: beqzc $[[R16]], $[[BB0]] ; MICROMIPS: beqzc $[[R16]], [[BB0]]
; MIPSR6: beqzc $[[R16]], $[[BB0]] ; MIPSR6: beqzc $[[R16]], [[BB0]]
; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 16 ; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 16
; NO-SEB-SEH: sra $2, $[[R19]], 16 ; NO-SEB-SEH: sra $2, $[[R19]], 16
; MIPS32R2: seh $2, $[[R18]] ; MIPS32R2: seh $2, $[[R18]]
Show All 12 Lines
; ALL-LABEL: foo ; ALL-LABEL: foo
; MIPSR6: addu $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]] ; MIPSR6: addu $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]]
; NOT-MICROMIPS: addu $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]] ; NOT-MICROMIPS: addu $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]]
; MICROMIPS: addu16 $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]] ; MICROMIPS: addu16 $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]]
; ALL: sync ; ALL: sync
; ALL: andi $[[R3:[0-9]+]], $[[R2]], 65535 ; ALL: andi $[[R3:[0-9]+]], $[[R2]], 65535
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R4:[0-9]+]], 0($[[R5:[0-9]+]]) ; ALL: ll $[[R4:[0-9]+]], 0($[[R5:[0-9]+]])
; ALL: and $[[R6:[0-9]+]], $[[R4]], $ ; ALL: and $[[R6:[0-9]+]], $[[R4]], $
; ALL: and $[[R7:[0-9]+]], $[[R4]], $ ; ALL: and $[[R7:[0-9]+]], $[[R4]], $
; ALL: or $[[R8:[0-9]+]], $[[R7]], $ ; ALL: or $[[R8:[0-9]+]], $[[R7]], $
; ALL: sc $[[R8]], 0($[[R5]]) ; ALL: sc $[[R8]], 0($[[R5]])
; NOT-MICROMIPS: beqz $[[R8]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R8]], [[BB0]]
; MICROMIPS: beqzc $[[R8]], $[[BB0]] ; MICROMIPS: beqzc $[[R8]], [[BB0]]
; MIPSR6: beqzc $[[R8]], $[[BB0]] ; MIPSR6: beqzc $[[R8]], [[BB0]]
; ALL: srlv $[[R9:[0-9]+]], $[[R6]], $ ; ALL: srlv $[[R9:[0-9]+]], $[[R6]], $
; NO-SEB-SEH: sll $[[R10:[0-9]+]], $[[R9]], 16 ; NO-SEB-SEH: sll $[[R10:[0-9]+]], $[[R9]], 16
; NO-SEB-SEH: sra $[[R11:[0-9]+]], $[[R10]], 16 ; NO-SEB-SEH: sra $[[R11:[0-9]+]], $[[R10]], 16
; NO-SEB-SEH: sll $[[R12:[0-9]+]], $[[R2]], 16 ; NO-SEB-SEH: sll $[[R12:[0-9]+]], $[[R2]], 16
; NO-SEB-SEH: sra $[[R13:[0-9]+]], $[[R12]], 16 ; NO-SEB-SEH: sra $[[R13:[0-9]+]], $[[R12]], 16
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Linesentry:
ret i32 %0 ret i32 %0
; ALL-LABEL: AtomicLoadAdd32_OffGt9Bit: ; ALL-LABEL: AtomicLoadAdd32_OffGt9Bit:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
; ALL: addiu $[[PTR:[0-9]+]], $[[R0]], 1024 ; ALL: addiu $[[PTR:[0-9]+]], $[[R0]], 1024
; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]:
; ALL: ll $[[R1:[0-9]+]], 0($[[PTR]]) ; ALL: ll $[[R1:[0-9]+]], 0($[[PTR]])
; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 ; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4
; ALL: sc $[[R2]], 0($[[PTR]]) ; ALL: sc $[[R2]], 0($[[PTR]])
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; NOT-MICROMIPS: beqz $[[R2]], [[BB0]]
; MICROMIPS: beqzc $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], [[BB0]]
; MIPSR6: beqzc $[[R2]], $[[BB0]] ; MIPSR6: beqzc $[[R2]], [[BB0]]
} }

llvm/trunk/test/CodeGen/Mips/blez_bgez.ll

; RUN: llc -march=mipsel < %s | FileCheck %s ; RUN: llc -march=mipsel < %s | FileCheck %s
; RUN: llc -march=mips64el < %s | FileCheck %s ; RUN: llc -march=mips64el < %s | FileCheck %s
; CHECK-LABEL: test_blez: ; CHECK-LABEL: test_blez:
; CHECK: blez ${{[0-9]+}}, $BB ; CHECK: blez ${{[0-9]+}}, {{\$|\.L}}BB
define void @test_blez(i32 %a) { define void @test_blez(i32 %a) {
entry: entry:
%cmp = icmp sgt i32 %a, 0 %cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
tail call void @foo1() tail call void @foo1()
br label %if.end br label %if.end
if.end: if.end:
ret void ret void
} }
declare void @foo1() declare void @foo1()
; CHECK-LABEL: test_bgez: ; CHECK-LABEL: test_bgez:
; CHECK: bgez ${{[0-9]+}}, $BB ; CHECK: bgez ${{[0-9]+}}, {{\$|\.L}}BB
define void @test_bgez(i32 %a) { define void @test_bgez(i32 %a) {
entry: entry:
%cmp = icmp slt i32 %a, 0 %cmp = icmp slt i32 %a, 0
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: if.then:
tail call void @foo1() tail call void @foo1()
br label %if.end br label %if.end
if.end: if.end:
ret void ret void
} }

llvm/trunk/test/CodeGen/Mips/blockaddr.ll

Show All 16 Lines
; PIC-O32: lw $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]]) ; PIC-O32: lw $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]])
; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]]) ; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]])
; PIC-O32: lw $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]]) ; PIC-O32: lw $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]])
; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]]) ; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]])
; STATIC-O32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]]) ; STATIC-O32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]])
; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]]) ; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]])
; STATIC-O32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]]) ; STATIC-O32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]])
; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]]) ; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
; PIC-N32: lw $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]]) ; PIC-N32: lw $[[R0:[0-9]+]], %got_page(.Ltmp[[T0:[0-9]+]])
; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]]) ; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst(.Ltmp[[T0]])
; PIC-N32: lw $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]]) ; PIC-N32: lw $[[R1:[0-9]+]], %got_page(.Ltmp[[T1:[0-9]+]])
; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]]) ; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst(.Ltmp[[T1]])
; STATIC-N32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]]) ; STATIC-N32: lui $[[R2:[0-9]+]], %hi(.Ltmp[[T2:[0-9]+]])
; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]]) ; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo(.Ltmp[[T2]])
; STATIC-N32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]]) ; STATIC-N32: lui $[[R3:[0-9]+]], %hi(.Ltmp[[T3:[0-9]+]])
; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]]) ; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo(.Ltmp[[T3]])
; PIC-N64: ld $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]]) ; PIC-N64: ld $[[R0:[0-9]+]], %got_page(.Ltmp[[T0:[0-9]+]])
; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]]) ; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst(.Ltmp[[T0]])
; PIC-N64: ld $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]]) ; PIC-N64: ld $[[R1:[0-9]+]], %got_page(.Ltmp[[T1:[0-9]+]])
; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]]) ; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst(.Ltmp[[T1]])
; STATIC-N64: ld $[[R2:[0-9]+]], %got_page($tmp[[T2:[0-9]+]]) ; STATIC-N64: ld $[[R2:[0-9]+]], %got_page(.Ltmp[[T2:[0-9]+]])
; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst($tmp[[T2]]) ; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst(.Ltmp[[T2]])
; STATIC-N64: ld $[[R3:[0-9]+]], %got_page($tmp[[T3:[0-9]+]]) ; STATIC-N64: ld $[[R3:[0-9]+]], %got_page(.Ltmp[[T3:[0-9]+]])
; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst($tmp[[T3]]) ; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst(.Ltmp[[T3]])
; STATIC-MIPS16-1: .ent f ; STATIC-MIPS16-1: .ent f
; STATIC-MIPS16-2: .ent f ; STATIC-MIPS16-2: .ent f
; STATIC-MIPS16-1: li $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]]) ; STATIC-MIPS16-1: li $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]])
; STATIC-MIPS16-1: sll ${{[0-9]+}}, $[[R1_16]], 16 ; STATIC-MIPS16-1: sll ${{[0-9]+}}, $[[R1_16]], 16
; STATIC-MIPS16-2: li ${{[0-9]+}}, %lo($tmp{{[0-9]+}}) ; STATIC-MIPS16-2: li ${{[0-9]+}}, %lo($tmp{{[0-9]+}})
; STATIC-MIPS16-1: jal dummy ; STATIC-MIPS16-1: jal dummy
; STATIC-MIPS16-2: jal dummy ; STATIC-MIPS16-2: jal dummy
Show All 13 Lines

llvm/trunk/test/CodeGen/Mips/ehframe-indirect.ll

Show All 27 Lines
; ALL: .cfi_endproc ; ALL: .cfi_endproc
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)
declare void @foo() declare void @foo()
; ALL: GCC_except_table{{[0-9]+}}: ; ALL: GCC_except_table{{[0-9]+}}:
; ALL: .byte 155 # @TType Encoding = indirect pcrel sdata4 ; ALL: .byte 155 # @TType Encoding = indirect pcrel sdata4
; ALL: $[[PC_LABEL:tmp[0-9]+]]: ; O32: [[PC_LABEL:\$tmp[0-9]+]]:
; ALL: .4byte ($_ZTISt9exception.DW.stub)-($[[PC_LABEL]]) ; N32: [[PC_LABEL:\.Ltmp[0-9]+]]:
; ALL: $_ZTISt9exception.DW.stub: ; N64: [[PC_LABEL:\.Ltmp[0-9]+]]:
; O32: .4byte ($_ZTISt9exception.DW.stub)-([[PC_LABEL]])
; N32: .4byte .L_ZTISt9exception.DW.stub-[[PC_LABEL]]
; N64: .4byte .L_ZTISt9exception.DW.stub-[[PC_LABEL]]
; O32: $_ZTISt9exception.DW.stub:
; N32: .L_ZTISt9exception.DW.stub:
; N64: .L_ZTISt9exception.DW.stub:
; O32: .4byte _ZTISt9exception ; O32: .4byte _ZTISt9exception
; N32: .4byte _ZTISt9exception ; N32: .4byte _ZTISt9exception
; N64: .8byte _ZTISt9exception ; N64: .8byte _ZTISt9exception
; ALL: .hidden DW.ref.__gxx_personality_v0 ; ALL: .hidden DW.ref.__gxx_personality_v0
; ALL: .weak DW.ref.__gxx_personality_v0 ; ALL: .weak DW.ref.__gxx_personality_v0
; ALL: .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat ; ALL: .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat
; O32: .p2align 2 ; O32: .p2align 2
; N32: .p2align 2 ; N32: .p2align 2
Show All 9 Lines

llvm/trunk/test/CodeGen/Mips/fcmp.ll

Show First 20 Lines • Show All 1,070 Lines • ▼ Show 20 Lines
; 32-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)( ; 32-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)(
; 32-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]] ; 32-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
; FIXME: This instruction is redundant. ; FIXME: This instruction is redundant.
; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
; 32-CMP-DAG: bnezc $[[T4]], ; 32-CMP-DAG: bnezc $[[T4]],
; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12
; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)( ; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)(
; 64-C-DAG: c.ole.s $[[T0]], $[[T1]] ; 64-C-DAG: c.ole.s $[[T0]], $[[T1]]
; 64-C-DAG: bc1t ; 64-C-DAG: bc1t
; 64-CMP-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)( ; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)(
; 64-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]] ; 64-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
; FIXME: This instruction is redundant. ; FIXME: This instruction is redundant.
; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
; 64-CMP-DAG: bnezc $[[T4]], ; 64-CMP-DAG: bnezc $[[T4]],
; MM32R3-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R3-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0) ; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)
; MM32R3-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]]) ; MM32R3-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
; MM32R3-DAG: c.ole.s $[[T0]], $[[T2]] ; MM32R3-DAG: c.ole.s $[[T0]], $[[T2]]
; MM32R3-DAG: bc1t ; MM32R3-DAG: bc1t
; MM32R6-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0) ; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)
; MM32R6-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]]) ; MM32R6-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]] ; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]] ; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]]
; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
; MM32R6-DAG: bnez $[[T5]], ; MM32R6-DAG: bnez $[[T5]],
; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32))) ; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32)))
; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 ; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25
; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32))) ; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32)))
; MM64R6-DAG: add.s $[[T3:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: add.s $[[T3:f[0-9]+]], $f13, $f12
; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI32_0)($[[T2]]) ; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page(.LCPI32_0)($[[T2]])
; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst($CPI32_0)($[[T4]]) ; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst(.LCPI32_0)($[[T4]])
; MM64R6-DAG: cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]] ; MM64R6-DAG: cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] ; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]]
; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 ; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1
; MM64R6-DAG: bnez $[[T8]], ; MM64R6-DAG: bnez $[[T8]],
%add = fadd fast float %at, %angle %add = fadd fast float %at, %angle
%cmp = fcmp ogt float %add, 1.000000e+00 %cmp = fcmp ogt float %add, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
Show All 21 Lines
; 32-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)( ; 32-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(
; 32-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]] ; 32-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
; FIXME: This instruction is redundant. ; FIXME: This instruction is redundant.
; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
; 32-CMP-DAG: bnezc $[[T4]], ; 32-CMP-DAG: bnezc $[[T4]],
; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)( ; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)(
; 64-C-DAG: c.ole.d $[[T0]], $[[T1]] ; 64-C-DAG: c.ole.d $[[T0]], $[[T1]]
; 64-C-DAG: bc1t ; 64-C-DAG: bc1t
; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)( ; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)(
; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]] ; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
; FIXME: This instruction is redundant. ; FIXME: This instruction is redundant.
; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
; 64-CMP-DAG: bnezc $[[T4]], ; 64-CMP-DAG: bnezc $[[T4]],
; MM32R3-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R3-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0) ; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
; MM32R3-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]]) ; MM32R3-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
; MM32R3-DAG: c.ole.d $[[T0]], $[[T2]] ; MM32R3-DAG: c.ole.d $[[T0]], $[[T2]]
; MM32R3-DAG: bc1t ; MM32R3-DAG: bc1t
; MM32R6-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0) ; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
; MM32R6-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]]) ; MM32R6-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]] ; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]] ; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]]
; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
; MM32R6-DAG: bnez $[[T5]], ; MM32R6-DAG: bnez $[[T5]],
; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64))) ; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64)))
; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 ; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25
; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64))) ; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64)))
; MM64R6-DAG: add.d $[[T3:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: add.d $[[T3:f[0-9]+]], $f13, $f12
; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI33_0)($[[T2]]) ; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page(.LCPI33_0)($[[T2]])
; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst($CPI33_0)($[[T4]]) ; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst(.LCPI33_0)($[[T4]])
; MM64R6-DAG: cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]] ; MM64R6-DAG: cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] ; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]]
; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 ; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1
; MM64R6-DAG: bnez $[[T8]], ; MM64R6-DAG: bnez $[[T8]],
%add = fadd fast double %at, %angle %add = fadd fast double %at, %angle
%cmp = fcmp ogt double %add, 1.000000e+00 %cmp = fcmp ogt double %add, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
Show All 11 Lines

llvm/trunk/test/CodeGen/Mips/fpbr.ll

; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC ; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC ; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC
; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
define void @func0(float %f2, float %f3) nounwind { define void @func0(float %f2, float %f3) nounwind {
entry: entry:
; ALL-LABEL: func0: ; ALL-LABEL: func0:
; 32-FCC: c.eq.s $f12, $f14 ; 32-FCC: c.eq.s $f12, $f14
; 32-FCC: bc1f $BB0_2
; 64-FCC: c.eq.s $f12, $f13 ; 64-FCC: c.eq.s $f12, $f13
; FCC: bc1f $BB0_2 ; 64-FCC: bc1f .LBB0_2
; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; FIXME: We ought to be able to transform not+bnez -> beqz ; FIXME: We ought to be able to transform not+bnez -> beqz
; GPR: not $[[GPRCC]], $[[GPRCC]] ; GPR: not $[[GPRCC]], $[[GPRCC]]
; 32-GPR: bnez $[[GPRCC]], $BB0_2 ; 32-GPR: bnez $[[GPRCC]], $BB0_2
; 64-GPR: bnezc $[[GPRCC]], $BB0_2 ; 64-GPR: bnezc $[[GPRCC]], .LBB0_2
%cmp = fcmp oeq float %f2, %f3 %cmp = fcmp oeq float %f2, %f3
br i1 %cmp, label %if.then, label %if.else br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void (...) @g0() nounwind tail call void (...) @g0() nounwind
br label %if.end br label %if.end
Show All 9 Lines
declare void @g1(...) declare void @g1(...)
define void @func1(float %f2, float %f3) nounwind { define void @func1(float %f2, float %f3) nounwind {
entry: entry:
; ALL-LABEL: func1: ; ALL-LABEL: func1:
; 32-FCC: c.olt.s $f12, $f14 ; 32-FCC: c.olt.s $f12, $f14
; 32-FCC: bc1f $BB1_2
; 64-FCC: c.olt.s $f12, $f13 ; 64-FCC: c.olt.s $f12, $f13
; FCC: bc1f $BB1_2 ; 64-FCC: bc1f .LBB1_2
; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; 32-GPR: bnez $[[GPRCC]], $BB1_2 ; 32-GPR: bnez $[[GPRCC]], $BB1_2
; 64-GPR: bnezc $[[GPRCC]], $BB1_2 ; 64-GPR: bnezc $[[GPRCC]], .LBB1_2
%cmp = fcmp olt float %f2, %f3 %cmp = fcmp olt float %f2, %f3
br i1 %cmp, label %if.then, label %if.else br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void (...) @g0() nounwind tail call void (...) @g0() nounwind
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
tail call void (...) @g1() nounwind tail call void (...) @g1() nounwind
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
ret void ret void
} }
define void @func2(float %f2, float %f3) nounwind { define void @func2(float %f2, float %f3) nounwind {
entry: entry:
; ALL-LABEL: func2: ; ALL-LABEL: func2:
; 32-FCC: c.ole.s $f12, $f14 ; 32-FCC: c.ole.s $f12, $f14
; 32-FCC: bc1t $BB2_2
; 64-FCC: c.ole.s $f12, $f13 ; 64-FCC: c.ole.s $f12, $f13
; FCC: bc1t $BB2_2 ; 64-FCC: bc1t .LBB2_2
; 32-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12 ; 32-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12
; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; 32-GPR: beqz $[[GPRCC]], $BB2_2 ; 32-GPR: beqz $[[GPRCC]], $BB2_2
; 64-GPR: beqzc $[[GPRCC]], $BB2_2 ; 64-GPR: beqzc $[[GPRCC]], .LBB2_2
%cmp = fcmp ugt float %f2, %f3 %cmp = fcmp ugt float %f2, %f3
br i1 %cmp, label %if.else, label %if.then br i1 %cmp, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void (...) @g0() nounwind tail call void (...) @g0() nounwind
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
tail call void (...) @g1() nounwind tail call void (...) @g1() nounwind
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
ret void ret void
} }
define void @func3(double %f2, double %f3) nounwind { define void @func3(double %f2, double %f3) nounwind {
entry: entry:
; ALL-LABEL: func3: ; ALL-LABEL: func3:
; 32-FCC: c.eq.d $f12, $f14 ; 32-FCC: c.eq.d $f12, $f14
; 32-FCC: bc1f $BB3_2
; 64-FCC: c.eq.d $f12, $f13 ; 64-FCC: c.eq.d $f12, $f13
; FCC: bc1f $BB3_2 ; 64-FCC: bc1f .LBB3_2
; 32-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14 ; 32-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14
; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13 ; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; FIXME: We ought to be able to transform not+bnez -> beqz ; FIXME: We ought to be able to transform not+bnez -> beqz
; GPR: not $[[GPRCC]], $[[GPRCC]] ; GPR: not $[[GPRCC]], $[[GPRCC]]
; 32-GPR: bnez $[[GPRCC]], $BB3_2 ; 32-GPR: bnez $[[GPRCC]], $BB3_2
; 64-GPR: bnezc $[[GPRCC]], $BB3_2 ; 64-GPR: bnezc $[[GPRCC]], .LBB3_2
%cmp = fcmp oeq double %f2, %f3 %cmp = fcmp oeq double %f2, %f3
br i1 %cmp, label %if.then, label %if.else br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void (...) @g0() nounwind tail call void (...) @g0() nounwind
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
tail call void (...) @g1() nounwind tail call void (...) @g1() nounwind
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
ret void ret void
} }
define void @func4(double %f2, double %f3) nounwind { define void @func4(double %f2, double %f3) nounwind {
entry: entry:
; ALL-LABEL: func4: ; ALL-LABEL: func4:
; 32-FCC: c.olt.d $f12, $f14 ; 32-FCC: c.olt.d $f12, $f14
; 32-FCC: bc1f $BB4_2
; 64-FCC: c.olt.d $f12, $f13 ; 64-FCC: c.olt.d $f12, $f13
; FCC: bc1f $BB4_2 ; 64-FCC: bc1f .LBB4_2
; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12 ; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12
; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; 32-GPR: bnez $[[GPRCC]], $BB4_2 ; 32-GPR: bnez $[[GPRCC]], $BB4_2
; 64-GPR: bnezc $[[GPRCC]], $BB4_2 ; 64-GPR: bnezc $[[GPRCC]], .LBB4_2
%cmp = fcmp olt double %f2, %f3 %cmp = fcmp olt double %f2, %f3
br i1 %cmp, label %if.then, label %if.else br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void (...) @g0() nounwind tail call void (...) @g0() nounwind
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
tail call void (...) @g1() nounwind tail call void (...) @g1() nounwind
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
ret void ret void
} }
define void @func5(double %f2, double %f3) nounwind { define void @func5(double %f2, double %f3) nounwind {
entry: entry:
; ALL-LABEL: func5: ; ALL-LABEL: func5:
; 32-FCC: c.ole.d $f12, $f14 ; 32-FCC: c.ole.d $f12, $f14
; 32-FCC: bc1t $BB5_2
; 64-FCC: c.ole.d $f12, $f13 ; 64-FCC: c.ole.d $f12, $f13
; FCC: bc1t $BB5_2 ; 64-FCC: bc1t .LBB5_2
; 32-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12 ; 32-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12
; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; 32-GPR: beqz $[[GPRCC]], $BB5_2 ; 32-GPR: beqz $[[GPRCC]], $BB5_2
; 64-GPR: beqzc $[[GPRCC]], $BB5_2 ; 64-GPR: beqzc $[[GPRCC]], .LBB5_2
%cmp = fcmp ugt double %f2, %f3 %cmp = fcmp ugt double %f2, %f3
br i1 %cmp, label %if.else, label %if.then br i1 %cmp, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
tail call void (...) @g0() nounwind tail call void (...) @g0() nounwind
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
tail call void (...) @g1() nounwind tail call void (...) @g1() nounwind
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
ret void ret void
} }

llvm/trunk/test/CodeGen/Mips/jumptable_labels.ll

; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32
; RUN: llc -march=mips64 -target-abi=n32 < %s | FileCheck %s -check-prefix=N32
; RUN: llc -march=mips64 < %s | FileCheck %s -check-prefix=N64
; We only use the '$' prefix on O32. The others use the ELF convention.
; O32: $JTI0_0
; N32: .LJTI0_0
; N64: .LJTI0_0
; Check basic block labels while we're at it.
; O32: $BB0_2:
; N32: .LBB0_2:
; N64: .LBB0_2:
@.str = private unnamed_addr constant [2 x i8] c"A\00", align 1
@.str.1 = private unnamed_addr constant [2 x i8] c"B\00", align 1
@.str.2 = private unnamed_addr constant [2 x i8] c"C\00", align 1
@.str.3 = private unnamed_addr constant [2 x i8] c"D\00", align 1
@.str.4 = private unnamed_addr constant [2 x i8] c"E\00", align 1
@.str.5 = private unnamed_addr constant [2 x i8] c"F\00", align 1
@.str.6 = private unnamed_addr constant [2 x i8] c"G\00", align 1
@.str.7 = private unnamed_addr constant [1 x i8] zeroinitializer, align 1
define i8* @_Z3fooi(i32 signext %Letter) {
entry:
%retval = alloca i8*, align 8
%Letter.addr = alloca i32, align 4
store i32 %Letter, i32* %Letter.addr, align 4
%0 = load i32, i32* %Letter.addr, align 4
switch i32 %0, label %sw.epilog [
i32 0, label %sw.bb
i32 1, label %sw.bb1
i32 2, label %sw.bb2
i32 3, label %sw.bb3
i32 4, label %sw.bb4
i32 5, label %sw.bb5
i32 6, label %sw.bb6
]
sw.bb:
store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i32 0, i32 0), i8** %retval, align 8
br label %return
sw.bb1:
store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.1, i32 0, i32 0), i8** %retval, align 8
br label %return
sw.bb2:
store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.2, i32 0, i32 0), i8** %retval, align 8
br label %return
sw.bb3:
store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.3, i32 0, i32 0), i8** %retval, align 8
br label %return
sw.bb4:
store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.4, i32 0, i32 0), i8** %retval, align 8
br label %return
sw.bb5:
store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.5, i32 0, i32 0), i8** %retval, align 8
br label %return
sw.bb6:
store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.6, i32 0, i32 0), i8** %retval, align 8
br label %return
sw.epilog:
store i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str.7, i32 0, i32 0), i8** %retval, align 8
br label %return
return:
%1 = load i8*, i8** %retval, align 8
ret i8* %1
}

llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
entry: entry:
; ALL-LABEL: ashr_i128: ; ALL-LABEL: ashr_i128:
; GP32: lw $25, %call16(__ashrti3)($gp) ; GP32: lw $25, %call16(__ashrti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrav $[[T1:[0-9]+]], $4, $7 ; M3: dsrav $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]]
; M3: move $3, $[[T1]] ; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]] ; M3: or $3, $[[T7]], $[[T4]]
; M3: $[[BB0]]: ; M3: [[BB0]]:
; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: beqz $[[T3]], [[BB1:.LBB[0-9_]+]]
; M3: nop ; M3: nop
; M3: dsra $2, $4, 63 ; M3: dsra $2, $4, 63
; M3: $[[BB1]]: ; M3: [[BB1]]:
; M3: jr $ra ; M3: jr $ra
; M3: nop ; M3: nop
; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
Show All 31 Lines

llvm/trunk/test/CodeGen/Mips/llvm-ir/indirectbr.ll

Show All 12 Lines
; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6
define i32 @br(i8 *%addr) { define i32 @br(i8 *%addr) {
; ALL-LABEL: br: ; ALL-LABEL: br:
; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR ; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR
; R6C: jrc $4 # <MCInst #{{[0-9]+}} JIC ; R6C: jrc $4 # <MCInst #{{[0-9]+}} JIC
; ALL: $BB0_1: # %L1 ; ALL: {{\$|\.L}}BB0_1: # %L1
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
; ALL: addiu $2, $zero, 0 ; ALL: addiu $2, $zero, 0
; ALL: $BB0_2: # %L2 ; ALL: {{\$|\.L}}BB0_2: # %L2
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
; ALL: addiu $2, $zero, 1 ; ALL: addiu $2, $zero, 1
entry: entry:
indirectbr i8* %addr, [label %L1, label %L2] indirectbr i8* %addr, [label %L1, label %L2]
L1: L1:
ret i32 0 ret i32 0
L2: L2:
ret i32 1 ret i32 1
} }

llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
entry: entry:
; ALL-LABEL: lshr_i128: ; ALL-LABEL: lshr_i128:
; GP32: lw $25, %call16(__lshrti3)($gp) ; GP32: lw $25, %call16(__lshrti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrlv $[[T1:[0-9]+]], $4, $7 ; M3: dsrlv $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]]
; M3: move $3, $[[T1]] ; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]] ; M3: or $3, $[[T7]], $[[T4]]
; M3: $[[BB0]]: ; M3: [[BB0]]:
; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: bnez $[[T3]], [[BB1:\.LBB[0-9_]+]]
; M3: daddiu $2, $zero, 0 ; M3: daddiu $2, $zero, 0
; M3: move $2, $[[T1]] ; M3: move $2, $[[T1]]
; M3: $[[BB1]]: ; M3: [[BB1]]:
; M3: jr $ra ; M3: jr $ra
; M3: nop ; M3: nop
; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
Show All 27 Lines

llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Linesentry:
; SEL-32: mtc1 $7, $[[F0:f[0-9]+]] ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
; SEL-32: mthc1 $6, $[[F0]] ; SEL-32: mthc1 $6, $[[F0]]
; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp) ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
; SEL-32: mtc1 $4, $f0 ; SEL-32: mtc1 $4, $f0
; SEL-32: sel.d $f0, $[[F1]], $[[F0]] ; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
; M3: andi $[[T0:[0-9]+]], $4, 1 ; M3: andi $[[T0:[0-9]+]], $4, 1
; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T0]], [[BB0:.LBB[0-9_]+]]
; M3: nop ; M3: nop
; M3: mov.d $f13, $f14 ; M3: mov.d $f13, $f14
; M3: $[[BB0]]: ; M3: [[BB0]]:
; M3: jr $ra ; M3: jr $ra
; M3: mov.d $f0, $f13 ; M3: mov.d $f0, $f13
; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
; CMOV-64: movn.d $f14, $f13, $[[T0]] ; CMOV-64: movn.d $f14, $f13, $[[T0]]
; CMOV-64: mov.d $f0, $f14 ; CMOV-64: mov.d $f0, $f14
; SEL-64: mtc1 $4, $f0 ; SEL-64: mtc1 $4, $f0
Show All 28 Linesentry:
; CMOV-32: movn.d $f14, $f12, $[[T1]] ; CMOV-32: movn.d $f14, $f12, $[[T1]]
; CMOV-32: mov.d $f0, $f14 ; CMOV-32: mov.d $f0, $f14
; SEL-32: lw $[[T0:[0-9]+]], 16($sp) ; SEL-32: lw $[[T0:[0-9]+]], 16($sp)
; SEL-32: mtc1 $[[T0]], $f0 ; SEL-32: mtc1 $[[T0]], $f0
; SEL-32: sel.d $f0, $f14, $f12 ; SEL-32: sel.d $f0, $f14, $f12
; M3: andi $[[T0:[0-9]+]], $6, 1 ; M3: andi $[[T0:[0-9]+]], $6, 1
; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
; M3: nop ; M3: nop
; M3: mov.d $f12, $f13 ; M3: mov.d $f12, $f13
; M3: $[[BB0]]: ; M3: [[BB0]]:
; M3: jr $ra ; M3: jr $ra
; M3: mov.d $f0, $f12 ; M3: mov.d $f0, $f12
; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
; CMOV-64: movn.d $f13, $f12, $[[T0]] ; CMOV-64: movn.d $f13, $f12, $[[T0]]
; CMOV-64: mov.d $f0, $f13 ; CMOV-64: mov.d $f0, $f13
; SEL-64: mtc1 $6, $f0 ; SEL-64: mtc1 $6, $f0
Show All 9 Lines
} }
define double @tst_select_fcmp_olt_double(double %x, double %y) { define double @tst_select_fcmp_olt_double(double %x, double %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_olt_double: ; ALL-LABEL: tst_select_fcmp_olt_double:
; M2: c.olt.d $f12, $f14 ; M2: c.olt.d $f12, $f14
; M3: c.olt.d $f12, $f13 ; M3: c.olt.d $f12, $f13
; M2-M3: bc1t $[[BB0:BB[0-9_]+]] ; M2: bc1t [[BB0:\$BB[0-9_]+]]
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.d $f12, $f14 ; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13 ; M3: mov.d $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12 ; M2-M3: mov.d $f0, $f12
; CMOV-32: c.olt.d $f12, $f14 ; CMOV-32: c.olt.d $f12, $f14
; CMOV-32: movt.d $f14, $f12, $fcc0 ; CMOV-32: movt.d $f14, $f12, $fcc0
; CMOV-32: mov.d $f0, $f14 ; CMOV-32: mov.d $f0, $f14
; SEL-32: cmp.lt.d $f0, $f12, $f14 ; SEL-32: cmp.lt.d $f0, $f12, $f14
Show All 16 Lines
} }
define double @tst_select_fcmp_ole_double(double %x, double %y) { define double @tst_select_fcmp_ole_double(double %x, double %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_ole_double: ; ALL-LABEL: tst_select_fcmp_ole_double:
; M2: c.ole.d $f12, $f14 ; M2: c.ole.d $f12, $f14
; M3: c.ole.d $f12, $f13 ; M3: c.ole.d $f12, $f13
; M2-M3: bc1t $[[BB0:BB[0-9_]+]] ; M2: bc1t [[BB0:\$BB[0-9_]+]]
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.d $f12, $f14 ; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13 ; M3: mov.d $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12 ; M2-M3: mov.d $f0, $f12
; CMOV-32: c.ole.d $f12, $f14 ; CMOV-32: c.ole.d $f12, $f14
; CMOV-32: movt.d $f14, $f12, $fcc0 ; CMOV-32: movt.d $f14, $f12, $fcc0
; CMOV-32: mov.d $f0, $f14 ; CMOV-32: mov.d $f0, $f14
; SEL-32: cmp.le.d $f0, $f12, $f14 ; SEL-32: cmp.le.d $f0, $f12, $f14
Show All 16 Lines
} }
define double @tst_select_fcmp_ogt_double(double %x, double %y) { define double @tst_select_fcmp_ogt_double(double %x, double %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_ogt_double: ; ALL-LABEL: tst_select_fcmp_ogt_double:
; M2: c.ule.d $f12, $f14 ; M2: c.ule.d $f12, $f14
; M3: c.ule.d $f12, $f13 ; M3: c.ule.d $f12, $f13
; M2-M3: bc1f $[[BB0:BB[0-9_]+]] ; M2: bc1f [[BB0:\$BB[0-9_]+]]
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.d $f12, $f14 ; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13 ; M3: mov.d $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12 ; M2-M3: mov.d $f0, $f12
; CMOV-32: c.ule.d $f12, $f14 ; CMOV-32: c.ule.d $f12, $f14
; CMOV-32: movf.d $f14, $f12, $fcc0 ; CMOV-32: movf.d $f14, $f12, $fcc0
; CMOV-32: mov.d $f0, $f14 ; CMOV-32: mov.d $f0, $f14
; SEL-32: cmp.lt.d $f0, $f14, $f12 ; SEL-32: cmp.lt.d $f0, $f14, $f12
Show All 16 Lines
} }
define double @tst_select_fcmp_oge_double(double %x, double %y) { define double @tst_select_fcmp_oge_double(double %x, double %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_oge_double: ; ALL-LABEL: tst_select_fcmp_oge_double:
; M2: c.ult.d $f12, $f14 ; M2: c.ult.d $f12, $f14
; M3: c.ult.d $f12, $f13 ; M3: c.ult.d $f12, $f13
; M2-M3: bc1f $[[BB0:BB[0-9_]+]] ; M2: bc1f [[BB0:\$BB[0-9_]+]]
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.d $f12, $f14 ; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13 ; M3: mov.d $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12 ; M2-M3: mov.d $f0, $f12
; CMOV-32: c.ult.d $f12, $f14 ; CMOV-32: c.ult.d $f12, $f14
; CMOV-32: movf.d $f14, $f12, $fcc0 ; CMOV-32: movf.d $f14, $f12, $fcc0
; CMOV-32: mov.d $f0, $f14 ; CMOV-32: mov.d $f0, $f14
; SEL-32: cmp.le.d $f0, $f14, $f12 ; SEL-32: cmp.le.d $f0, $f14, $f12
Show All 16 Lines
} }
define double @tst_select_fcmp_oeq_double(double %x, double %y) { define double @tst_select_fcmp_oeq_double(double %x, double %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_oeq_double: ; ALL-LABEL: tst_select_fcmp_oeq_double:
; M2: c.eq.d $f12, $f14 ; M2: c.eq.d $f12, $f14
; M3: c.eq.d $f12, $f13 ; M3: c.eq.d $f12, $f13
; M2-M3: bc1t $[[BB0:BB[0-9_]+]] ; M2: bc1t [[BB0:\$BB[0-9_]+]]
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.d $f12, $f14 ; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13 ; M3: mov.d $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12 ; M2-M3: mov.d $f0, $f12
; CMOV-32: c.eq.d $f12, $f14 ; CMOV-32: c.eq.d $f12, $f14
; CMOV-32: movt.d $f14, $f12, $fcc0 ; CMOV-32: movt.d $f14, $f12, $fcc0
; CMOV-32: mov.d $f0, $f14 ; CMOV-32: mov.d $f0, $f14
; SEL-32: cmp.eq.d $f0, $f12, $f14 ; SEL-32: cmp.eq.d $f0, $f12, $f14
Show All 16 Lines
} }
define double @tst_select_fcmp_one_double(double %x, double %y) { define double @tst_select_fcmp_one_double(double %x, double %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_one_double: ; ALL-LABEL: tst_select_fcmp_one_double:
; M2: c.ueq.d $f12, $f14 ; M2: c.ueq.d $f12, $f14
; M3: c.ueq.d $f12, $f13 ; M3: c.ueq.d $f12, $f13
; M2-M3: bc1f $[[BB0:BB[0-9_]+]] ; M2: bc1f [[BB0:\$BB[0-9_]+]]
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.d $f12, $f14 ; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13 ; M3: mov.d $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12 ; M2-M3: mov.d $f0, $f12
; CMOV-32: c.ueq.d $f12, $f14 ; CMOV-32: c.ueq.d $f12, $f14
; CMOV-32: movf.d $f14, $f12, $fcc0 ; CMOV-32: movf.d $f14, $f12, $fcc0
; CMOV-32: mov.d $f0, $f14 ; CMOV-32: mov.d $f0, $f14
; SEL-32: cmp.ueq.d $f0, $f12, $f14 ; SEL-32: cmp.ueq.d $f0, $f12, $f14
Show All 23 Lines

llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll

Show All 28 Lines
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM32R6,SEL-32 ; RUN: -check-prefixes=ALL,MM32R6,SEL-32
define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
entry: entry:
; ALL-LABEL: tst_select_i1_float: ; ALL-LABEL: tst_select_i1_float:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: jr $ra ; M2: jr $ra
; M2: mtc1 $6, $f0 ; M2: mtc1 $6, $f0
; M3: mov.s $f13, $f14 ; M3: mov.s $f13, $f14
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2: mtc1 $5, $f0 ; M2: mtc1 $5, $f0
; M3: mov.s $f0, $f13 ; M3: mov.s $f0, $f13
; CMOV-32: mtc1 $6, $f0 ; CMOV-32: mtc1 $6, $f0
; CMOV-32: mtc1 $5, $f1 ; CMOV-32: mtc1 $5, $f1
; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
; CMOV-32: movn.s $f0, $f1, $[[T0]] ; CMOV-32: movn.s $f0, $f1, $[[T0]]
Show All 20 Lines
} }
define float @tst_select_i1_float_reordered(float %x, float %y, define float @tst_select_i1_float_reordered(float %x, float %y,
i1 signext %s) { i1 signext %s) {
entry: entry:
; ALL-LABEL: tst_select_i1_float_reordered: ; ALL-LABEL: tst_select_i1_float_reordered:
; M2-M3: andi $[[T0:[0-9]+]], $6, 1 ; M2-M3: andi $[[T0:[0-9]+]], $6, 1
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.s $f12, $f14 ; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13 ; M3: mov.s $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12 ; M2-M3: mov.s $f0, $f12
; CMOV-32: andi $[[T0:[0-9]+]], $6, 1 ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
; CMOV-32: movn.s $f14, $f12, $[[T0]] ; CMOV-32: movn.s $f14, $f12, $[[T0]]
; CMOV-32: mov.s $f0, $f14 ; CMOV-32: mov.s $f0, $f14
; SEL-32: mtc1 $6, $f0 ; SEL-32: mtc1 $6, $f0
Show All 15 Lines
} }
define float @tst_select_fcmp_olt_float(float %x, float %y) { define float @tst_select_fcmp_olt_float(float %x, float %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_olt_float: ; ALL-LABEL: tst_select_fcmp_olt_float:
; M2: c.olt.s $f12, $f14 ; M2: c.olt.s $f12, $f14
; M3: c.olt.s $f12, $f13 ; M3: c.olt.s $f12, $f13
; M2-M3: bc1t $[[BB0:BB[0-9_]+]] ; M2: bc1t [[BB0:\$BB[0-9_]+]]
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.s $f12, $f14 ; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13 ; M3: mov.s $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12 ; M2-M3: mov.s $f0, $f12
; CMOV-32: c.olt.s $f12, $f14 ; CMOV-32: c.olt.s $f12, $f14
; CMOV-32: movt.s $f14, $f12, $fcc0 ; CMOV-32: movt.s $f14, $f12, $fcc0
; CMOV-32: mov.s $f0, $f14 ; CMOV-32: mov.s $f0, $f14
; SEL-32: cmp.lt.s $f0, $f12, $f14 ; SEL-32: cmp.lt.s $f0, $f12, $f14
Show All 16 Lines
} }
define float @tst_select_fcmp_ole_float(float %x, float %y) { define float @tst_select_fcmp_ole_float(float %x, float %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_ole_float: ; ALL-LABEL: tst_select_fcmp_ole_float:
; M2: c.ole.s $f12, $f14 ; M2: c.ole.s $f12, $f14
; M3: c.ole.s $f12, $f13 ; M3: c.ole.s $f12, $f13
; M2-M3: bc1t $[[BB0:BB[0-9_]+]] ; M2: bc1t [[BB0:\$BB[0-9_]+]]
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.s $f12, $f14 ; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13 ; M3: mov.s $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12 ; M2-M3: mov.s $f0, $f12
; CMOV-32: c.ole.s $f12, $f14 ; CMOV-32: c.ole.s $f12, $f14
; CMOV-32: movt.s $f14, $f12, $fcc0 ; CMOV-32: movt.s $f14, $f12, $fcc0
; CMOV-32: mov.s $f0, $f14 ; CMOV-32: mov.s $f0, $f14
; SEL-32: cmp.le.s $f0, $f12, $f14 ; SEL-32: cmp.le.s $f0, $f12, $f14
Show All 16 Lines
} }
define float @tst_select_fcmp_ogt_float(float %x, float %y) { define float @tst_select_fcmp_ogt_float(float %x, float %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_ogt_float: ; ALL-LABEL: tst_select_fcmp_ogt_float:
; M2: c.ule.s $f12, $f14 ; M2: c.ule.s $f12, $f14
; M3: c.ule.s $f12, $f13 ; M3: c.ule.s $f12, $f13
; M2-M3: bc1f $[[BB0:BB[0-9_]+]] ; M2: bc1f [[BB0:\$BB[0-9_]+]]
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.s $f12, $f14 ; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13 ; M3: mov.s $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12 ; M2-M3: mov.s $f0, $f12
; CMOV-32: c.ule.s $f12, $f14 ; CMOV-32: c.ule.s $f12, $f14
; CMOV-32: movf.s $f14, $f12, $fcc0 ; CMOV-32: movf.s $f14, $f12, $fcc0
; CMOV-32: mov.s $f0, $f14 ; CMOV-32: mov.s $f0, $f14
; SEL-32: cmp.lt.s $f0, $f14, $f12 ; SEL-32: cmp.lt.s $f0, $f14, $f12
Show All 16 Lines
} }
define float @tst_select_fcmp_oge_float(float %x, float %y) { define float @tst_select_fcmp_oge_float(float %x, float %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_oge_float: ; ALL-LABEL: tst_select_fcmp_oge_float:
; M2: c.ult.s $f12, $f14 ; M2: c.ult.s $f12, $f14
; M3: c.ult.s $f12, $f13 ; M3: c.ult.s $f12, $f13
; M2-M3: bc1f $[[BB0:BB[0-9_]+]] ; M2: bc1f [[BB0:\$BB[0-9_]+]]
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.s $f12, $f14 ; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13 ; M3: mov.s $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12 ; M2-M3: mov.s $f0, $f12
; CMOV-32: c.ult.s $f12, $f14 ; CMOV-32: c.ult.s $f12, $f14
; CMOV-32: movf.s $f14, $f12, $fcc0 ; CMOV-32: movf.s $f14, $f12, $fcc0
; CMOV-32: mov.s $f0, $f14 ; CMOV-32: mov.s $f0, $f14
; SEL-32: cmp.le.s $f0, $f14, $f12 ; SEL-32: cmp.le.s $f0, $f14, $f12
Show All 16 Lines
} }
define float @tst_select_fcmp_oeq_float(float %x, float %y) { define float @tst_select_fcmp_oeq_float(float %x, float %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_oeq_float: ; ALL-LABEL: tst_select_fcmp_oeq_float:
; M2: c.eq.s $f12, $f14 ; M2: c.eq.s $f12, $f14
; M3: c.eq.s $f12, $f13 ; M3: c.eq.s $f12, $f13
; M2-M3: bc1t $[[BB0:BB[0-9_]+]] ; M2: bc1t [[BB0:\$BB[0-9_]+]]
; M3: bc1t [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.s $f12, $f14 ; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13 ; M3: mov.s $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12 ; M2-M3: mov.s $f0, $f12
; CMOV-32: c.eq.s $f12, $f14 ; CMOV-32: c.eq.s $f12, $f14
; CMOV-32: movt.s $f14, $f12, $fcc0 ; CMOV-32: movt.s $f14, $f12, $fcc0
; CMOV-32: mov.s $f0, $f14 ; CMOV-32: mov.s $f0, $f14
; SEL-32: cmp.eq.s $f0, $f12, $f14 ; SEL-32: cmp.eq.s $f0, $f12, $f14
Show All 16 Lines
} }
define float @tst_select_fcmp_one_float(float %x, float %y) { define float @tst_select_fcmp_one_float(float %x, float %y) {
entry: entry:
; ALL-LABEL: tst_select_fcmp_one_float: ; ALL-LABEL: tst_select_fcmp_one_float:
; M2: c.ueq.s $f12, $f14 ; M2: c.ueq.s $f12, $f14
; M3: c.ueq.s $f12, $f13 ; M3: c.ueq.s $f12, $f13
; M2-M3: bc1f $[[BB0:BB[0-9_]+]] ; M2: bc1f [[BB0:\$BB[0-9_]+]]
; M3: bc1f [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2: mov.s $f12, $f14 ; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13 ; M3: mov.s $f12, $f13
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12 ; M2-M3: mov.s $f0, $f12
; CMOV-32: c.ueq.s $f12, $f14 ; CMOV-32: c.ueq.s $f12, $f14
; CMOV-32: movf.s $f14, $f12, $fcc0 ; CMOV-32: movf.s $f14, $f12, $fcc0
; CMOV-32: mov.s $f0, $f14 ; CMOV-32: mov.s $f0, $f14
; SEL-32: cmp.ueq.s $f0, $f12, $f14 ; SEL-32: cmp.ueq.s $f0, $f12, $f14
Show All 23 Lines

llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll

Show All 29 Lines
; RUN: -check-prefixes=ALL,MMR6,MM32R6 ; RUN: -check-prefixes=ALL,MMR6,MM32R6
define signext i1 @tst_select_i1_i1(i1 signext %s, define signext i1 @tst_select_i1_i1(i1 signext %s,
i1 signext %x, i1 signext %y) { i1 signext %x, i1 signext %y) {
entry: entry:
; ALL-LABEL: tst_select_i1_i1: ; ALL-LABEL: tst_select_i1_i1:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2-M3: move $5, $6 ; M2-M3: move $5, $6
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: move $2, $5 ; M2-M3: move $2, $5
; CMOV: andi $[[T0:[0-9]+]], $4, 1 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
; CMOV: movn $6, $5, $[[T0]] ; CMOV: movn $6, $5, $[[T0]]
; CMOV: move $2, $6 ; CMOV: move $2, $6
; SEL: andi $[[T0:[0-9]+]], $4, 1 ; SEL: andi $[[T0:[0-9]+]], $4, 1
Show All 15 Lines
} }
define signext i8 @tst_select_i1_i8(i1 signext %s, define signext i8 @tst_select_i1_i8(i1 signext %s,
i8 signext %x, i8 signext %y) { i8 signext %x, i8 signext %y) {
entry: entry:
; ALL-LABEL: tst_select_i1_i8: ; ALL-LABEL: tst_select_i1_i8:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2-M3: move $5, $6 ; M2-M3: move $5, $6
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: move $2, $5 ; M2-M3: move $2, $5
; CMOV: andi $[[T0:[0-9]+]], $4, 1 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
; CMOV: movn $6, $5, $[[T0]] ; CMOV: movn $6, $5, $[[T0]]
; CMOV: move $2, $6 ; CMOV: move $2, $6
; SEL: andi $[[T0:[0-9]+]], $4, 1 ; SEL: andi $[[T0:[0-9]+]], $4, 1
Show All 15 Lines
} }
define signext i32 @tst_select_i1_i32(i1 signext %s, define signext i32 @tst_select_i1_i32(i1 signext %s,
i32 signext %x, i32 signext %y) { i32 signext %x, i32 signext %y) {
entry: entry:
; ALL-LABEL: tst_select_i1_i32: ; ALL-LABEL: tst_select_i1_i32:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
; M2-M3: nop ; M2-M3: nop
; M2-M3: move $5, $6 ; M2-M3: move $5, $6
; M2-M3: $[[BB0]]: ; M2-M3: [[BB0]]:
; M2-M3: jr $ra ; M2-M3: jr $ra
; M2-M3: move $2, $5 ; M2-M3: move $2, $5
; CMOV: andi $[[T0:[0-9]+]], $4, 1 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
; CMOV: movn $6, $5, $[[T0]] ; CMOV: movn $6, $5, $[[T0]]
; CMOV: move $2, $6 ; CMOV: move $2, $6
; SEL: andi $[[T0:[0-9]+]], $4, 1 ; SEL: andi $[[T0:[0-9]+]], $4, 1
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesentry:
; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]] ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
; SEL-32: or $2, $[[T1]], $[[T3]] ; SEL-32: or $2, $[[T1]], $[[T3]]
; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]] ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]]
; SEL-32: lw $[[T5:[0-9]+]], 20($sp) ; SEL-32: lw $[[T5:[0-9]+]], 20($sp)
; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]] ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]]
; SEL-32: or $3, $[[T4]], $[[T6]] ; SEL-32: or $3, $[[T4]], $[[T6]]
; M3: andi $[[T0:[0-9]+]], $4, 1 ; M3: andi $[[T0:[0-9]+]], $4, 1
; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
; M3: nop ; M3: nop
; M3: move $5, $6 ; M3: move $5, $6
; M3: $[[BB0]]: ; M3: [[BB0]]:
; M3: jr $ra ; M3: jr $ra
; M3: move $2, $5 ; M3: move $2, $5
; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
; CMOV-64: movn $6, $5, $[[T0]] ; CMOV-64: movn $6, $5, $[[T0]]
; CMOV-64: move $2, $6 ; CMOV-64: move $2, $6
; SEL-64: andi $[[T0:[0-9]+]], $4, 1 ; SEL-64: andi $[[T0:[0-9]+]], $4, 1
Show All 24 Lines
} }
define i8* @tst_select_word_cst(i8* %a, i8* %b) { define i8* @tst_select_word_cst(i8* %a, i8* %b) {
; ALL-LABEL: tst_select_word_cst: ; ALL-LABEL: tst_select_word_cst:
; M2: addiu $[[T0:[0-9]+]], $zero, -1 ; M2: addiu $[[T0:[0-9]+]], $zero, -1
; M2: xor $[[T1:[0-9]+]], $5, $[[T0]] ; M2: xor $[[T1:[0-9]+]], $5, $[[T0]]
; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]] ; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; M2: bnez $[[T2]], $[[BB0:BB[0-9_]+]] ; M2: bnez $[[T2]], [[BB0:\$BB[0-9_]+]]
; M2: addiu $2, $zero, 0 ; M2: addiu $2, $zero, 0
; M2: move $2, $4 ; M2: move $2, $4
; M2: $[[BB0]]: ; M2: [[BB0]]:
; M2: jr $ra ; M2: jr $ra
; M3: daddiu $[[T0:[0-9]+]], $zero, -1 ; M3: daddiu $[[T0:[0-9]+]], $zero, -1
; M3: xor $[[T1:[0-9]+]], $5, $[[T0]] ; M3: xor $[[T1:[0-9]+]], $5, $[[T0]]
; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]] ; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; M3: bnez $[[T2]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T2]], [[BB0:\.LBB[0-9_]+]]
; M3: daddiu $2, $zero, 0 ; M3: daddiu $2, $zero, 0
; M3: move $2, $4 ; M3: move $2, $4
; M3: $[[BB0]]: ; M3: [[BB0]]:
; M3: jr $ra ; M3: jr $ra
; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1 ; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1
; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]] ; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]] ; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]]
; CMOV-32: jr $ra ; CMOV-32: jr $ra
; CMOV-32: move $2, $[[T2]] ; CMOV-32: move $2, $[[T2]]
Show All 33 Lines

llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll

Show First 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
entry: entry:
; ALL-LABEL: shl_i128: ; ALL-LABEL: shl_i128:
; GP32: lw $25, %call16(__ashlti3)($gp) ; GP32: lw $25, %call16(__ashlti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsllv $[[T1:[0-9]+]], $5, $7 ; M3: dsllv $[[T1:[0-9]+]], $5, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: bnez $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]]
; M3: move $2, $[[T1]] ; M3: move $2, $[[T1]]
; M3: dsllv $[[T4:[0-9]+]], $4, $7 ; M3: dsllv $[[T4:[0-9]+]], $4, $7
; M3: dsrl $[[T5:[0-9]+]], $5, 1 ; M3: dsrl $[[T5:[0-9]+]], $5, 1
; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $2, $[[T4]], $[[T7]] ; M3: or $2, $[[T4]], $[[T7]]
; M3: $[[BB0]]: ; M3: [[BB0]]:
; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: bnez $[[T3]], [[BB1:\.LBB[0-9_]+]]
; M3: daddiu $3, $zero, 0 ; M3: daddiu $3, $zero, 0
; M3: move $3, $[[T1]] ; M3: move $3, $[[T1]]
; M3: $[[BB1]]: ; M3: [[BB1]]:
; M3: jr $ra ; M3: jr $ra
; M3: nop ; M3: nop
; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7 ; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7
; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1 ; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1
; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]] ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
Show All 27 Lines

llvm/trunk/test/CodeGen/Mips/longbranch.ll

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; In MIPS32R6 JR is an alias to JALR with $rd=0. As everything else remains the ; In MIPS32R6 JR is an alias to JALR with $rd=0. As everything else remains the
; same with the O32 prefix, we use -asm-show-inst in order to make sure that ; same with the O32 prefix, we use -asm-show-inst in order to make sure that
; the opcode of the MachineInst is a JALR. ; the opcode of the MachineInst is a JALR.
; O32-R6: JALR ; O32-R6: JALR
; Check the MIPS64 version. ; Check the MIPS64 version.
; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1))) ; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1)))
; N64: bnez $4, $[[BB0:BB[0-9_]+]] ; N64: bnez $4, [[BB0:\.LBB[0-9_]+]]
; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25 ; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25
; Check for long branch expansion: ; Check for long branch expansion:
; N64: daddiu $sp, $sp, -16 ; N64: daddiu $sp, $sp, -16
; N64-NEXT: sd $ra, 0($sp) ; N64-NEXT: sd $ra, 0($sp)
; N64-NEXT: daddiu $1, $zero, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) ; N64-NEXT: daddiu $1, $zero, %hi([[BB2:\.LBB[0-9_]+]]-[[BB1:\.LBB[0-9_]+]])
; N64-NEXT: dsll $1, $1, 16 ; N64-NEXT: dsll $1, $1, 16
; N64-NEXT: bal $[[BB1]] ; N64-NEXT: bal [[BB1]]
; N64-NEXT: daddiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) ; N64-NEXT: daddiu $1, $1, %lo([[BB2]]-[[BB1]])
; N64-NEXT: $[[BB1]]: ; N64-NEXT: [[BB1]]:
; N64-NEXT: daddu $1, $ra, $1 ; N64-NEXT: daddu $1, $ra, $1
; N64-NEXT: ld $ra, 0($sp) ; N64-NEXT: ld $ra, 0($sp)
; N64-NEXT: jr $1 ; N64-NEXT: jr $1
; N64-NEXT: daddiu $sp, $sp, 16 ; N64-NEXT: daddiu $sp, $sp, 16
; N64: $[[BB0]]: ; N64: [[BB0]]:
; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1))) ; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1)))
; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
; N64: addiu $[[R3:[0-9]+]], $zero, 1 ; N64: addiu $[[R3:[0-9]+]], $zero, 1
; N64: sw $[[R3]], 0($[[R2]]) ; N64: sw $[[R3]], 0($[[R2]])
; N64: $[[BB2]]: ; N64: [[BB2]]:
; N64: jr $ra ; N64: jr $ra
; N64: nop ; N64: nop
; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the ; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the
; same with the N64 prefix, we use -asm-show-inst in order to make sure that ; same with the N64 prefix, we use -asm-show-inst in order to make sure that
; the opcode of the MachineInst is a JALR. ; the opcode of the MachineInst is a JALR.
; N64-R6: JALR64 ; N64-R6: JALR64
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/msa/basic_operations.ll

Show All 30 Linesdefine void @const_v16i8() nounwind {
store volatile <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>*@v16i8 store volatile <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>*@v16i8
; ALL: ldi.b [[R1:\$w[0-9]+]], 0 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8>*@v16i8 store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8>*@v16i8
; ALL: ldi.b [[R1:\$w[0-9]+]], 1 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8 store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8 store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8
; ALL-BE: ldi.h [[R1:\$w[0-9]+]], 256 ; ALL-BE: ldi.h [[R1:\$w[0-9]+]], 256
; ALL-LE: ldi.h [[R1:\$w[0-9]+]], 1 ; ALL-LE: ldi.h [[R1:\$w[0-9]+]], 1
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8
; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 258 ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 258
; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 1027 ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 1027
; ALL-BE-DAG: ori [[R2]], [[R2]], 772 ; ALL-BE-DAG: ori [[R2]], [[R2]], 772
; ALL-LE-DAG: ori [[R2]], [[R2]], 513 ; ALL-LE-DAG: ori [[R2]], [[R2]], 513
; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8 store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
} }
define void @const_v8i16() nounwind { define void @const_v8i16() nounwind {
; ALL-LABEL: const_v8i16: ; ALL-LABEL: const_v8i16:
store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16 store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16
; ALL: ldi.b [[R1:\$w[0-9]+]], 0 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16>*@v8i16 store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16>*@v8i16
; ALL: ldi.h [[R1:\$w[0-9]+]], 1 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16 store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16 store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16
; ALL: ldi.b [[R1:\$w[0-9]+]], 4 ; ALL: ldi.b [[R1:\$w[0-9]+]], 4
store volatile <8 x i16> <i16 1, i16 2, i16 1, i16 2, i16 1, i16 2, i16 1, i16 2>, <8 x i16>*@v8i16 store volatile <8 x i16> <i16 1, i16 2, i16 1, i16 2, i16 1, i16 2, i16 1, i16 2>, <8 x i16>*@v8i16
; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 1 ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 1
; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 2 ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 2
; ALL-BE-DAG: ori [[R2]], [[R2]], 2 ; ALL-BE-DAG: ori [[R2]], [[R2]], 2
; ALL-LE-DAG: ori [[R2]], [[R2]], 1 ; ALL-LE-DAG: ori [[R2]], [[R2]], 1
; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16 store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
} }
define void @const_v4i32() nounwind { define void @const_v4i32() nounwind {
; ALL-LABEL: const_v4i32: ; ALL-LABEL: const_v4i32:
store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32 store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32
; ALL: ldi.b [[R1:\$w[0-9]+]], 0 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>*@v4i32 store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>*@v4i32
; ALL: ldi.w [[R1:\$w[0-9]+]], 1 ; ALL: ldi.w [[R1:\$w[0-9]+]], 1
store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32 store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32 store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32
; ALL: ldi.b [[R1:\$w[0-9]+]], 1 ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
store volatile <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537>, <4 x i32>*@v4i32 store volatile <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537>, <4 x i32>*@v4i32
; ALL: ldi.h [[R1:\$w[0-9]+]], 1 ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32 store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32 store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
} }
define void @const_v2i64() nounwind { define void @const_v2i64() nounwind {
; ALL-LABEL: const_v2i64: ; ALL-LABEL: const_v2i64:
Show All 9 Linesdefine void @const_v2i64() nounwind {
store volatile <2 x i64> <i64 4294967297, i64 4294967297>, <2 x i64>*@v2i64 store volatile <2 x i64> <i64 4294967297, i64 4294967297>, <2 x i64>*@v2i64
; ALL: ldi.w [[R1:\$w[0-9]+]], 1 ; ALL: ldi.w [[R1:\$w[0-9]+]], 1
store volatile <2 x i64> <i64 1, i64 1>, <2 x i64>*@v2i64 store volatile <2 x i64> <i64 1, i64 1>, <2 x i64>*@v2i64
; ALL: ldi.d [[R1:\$w[0-9]+]], 1 ; ALL: ldi.d [[R1:\$w[0-9]+]], 1
store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64 store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64 store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
} }
define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind { define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind {
; ALL-LABEL: nonconst_v16i8: ; ALL-LABEL: nonconst_v16i8:
▲ Show 20 Lines • Show All 703 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/msa/basic_operations_float.ll

Show All 17 Linesdefine void @const_v4f32() nounwind {
; ALL: ldi.b [[R1:\$w[0-9]+]], 0 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
; ALL: lui [[R1:\$[0-9]+]], 16256 ; ALL: lui [[R1:\$[0-9]+]], 16256
; ALL: fill.w [[R2:\$w[0-9]+]], [[R1]] ; ALL: fill.w [[R2:\$w[0-9]+]], [[R1]]
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32 store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
; ALL: lui [[R1:\$[0-9]+]], 18304 ; ALL: lui [[R1:\$[0-9]+]], 18304
; ALL: ori [[R2:\$[0-9]+]], [[R1]], 128 ; ALL: ori [[R2:\$[0-9]+]], [[R1]], 128
; ALL: fill.w [[R3:\$w[0-9]+]], [[R2]] ; ALL: fill.w [[R3:\$w[0-9]+]], [[R2]]
store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32 store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32 store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
} }
define void @const_v2f64() nounwind { define void @const_v2f64() nounwind {
; ALL-LABEL: const_v2f64: ; ALL-LABEL: const_v2f64:
store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64 store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
; ALL: ldi.b [[R1:\$w[0-9]+]], 0 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64 store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64 store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64 store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64 store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64 store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64 store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L
; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
ret void ret void
} }
define void @nonconst_v4f32() nounwind { define void @nonconst_v4f32() nounwind {
; ALL-LABEL: nonconst_v4f32: ; ALL-LABEL: nonconst_v4f32:
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/octeon.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines; MIPS64: dsrl $2, $[[T3]], 32
%res = icmp ne i64 %a, 42 %res = icmp ne i64 %a, 42
%res2 = zext i1 %res to i64 %res2 = zext i1 %res to i64
ret i64 %res2 ret i64 %res2
} }
define i64 @bbit0(i64 %a) nounwind { define i64 @bbit0(i64 %a) nounwind {
entry: entry:
; ALL-LABEL: bbit0: ; ALL-LABEL: bbit0:
; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]] ; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; MIPS64: andi $[[T0:[0-9]+]], $4, 8 ; MIPS64: andi $[[T0:[0-9]+]], $4, 8
; MIPS64: bnez $[[T0]], $[[BB0:BB[0-9_]+]] ; MIPS64: bnez $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
%bit = and i64 %a, 8 %bit = and i64 %a, 8
%res = icmp eq i64 %bit, 0 %res = icmp eq i64 %bit, 0
br i1 %res, label %endif, label %if br i1 %res, label %endif, label %if
if: if:
ret i64 48 ret i64 48
endif: endif:
ret i64 12 ret i64 12
} }
define i64 @bbit032(i64 %a) nounwind { define i64 @bbit032(i64 %a) nounwind {
entry: entry:
; ALL-LABEL: bbit032: ; ALL-LABEL: bbit032:
; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]] ; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 ; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] ; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
; MIPS64: bnez $[[T2]], $[[BB0:BB[0-9_]+]] ; MIPS64: bnez $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]]
%bit = and i64 %a, 34359738368 %bit = and i64 %a, 34359738368
%res = icmp eq i64 %bit, 0 %res = icmp eq i64 %bit, 0
br i1 %res, label %endif, label %if br i1 %res, label %endif, label %if
if: if:
ret i64 48 ret i64 48
endif: endif:
ret i64 12 ret i64 12
} }
define i64 @bbit1(i64 %a) nounwind { define i64 @bbit1(i64 %a) nounwind {
entry: entry:
; ALL-LABEL: bbit1: ; ALL-LABEL: bbit1:
; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]] ; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; MIPS64: andi $[[T0:[0-9]+]], $4, 8 ; MIPS64: andi $[[T0:[0-9]+]], $4, 8
; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]] ; MIPS64: beqz $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
%bit = and i64 %a, 8 %bit = and i64 %a, 8
%res = icmp ne i64 %bit, 0 %res = icmp ne i64 %bit, 0
br i1 %res, label %endif, label %if br i1 %res, label %endif, label %if
if: if:
ret i64 48 ret i64 48
endif: endif:
ret i64 12 ret i64 12
} }
define i64 @bbit132(i64 %a) nounwind { define i64 @bbit132(i64 %a) nounwind {
entry: entry:
; ALL-LABEL: bbit132: ; ALL-LABEL: bbit132:
; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]] ; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 ; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] ; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]] ; MIPS64: beqz $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]]
%bit = and i64 %a, 34359738368 %bit = and i64 %a, 34359738368
%res = icmp ne i64 %bit, 0 %res = icmp ne i64 %bit, 0
br i1 %res, label %endif, label %if br i1 %res, label %endif, label %if
if: if:
ret i64 48 ret i64 48
endif: endif:
ret i64 12 ret i64 12
} }

llvm/trunk/test/MC/Mips/cpsetup.s

# RUN: llvm-mc -triple mips64-unknown-linux -target-abi o32 -filetype=obj -o - %s | \ # RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 -filetype=obj -o - %s | \
# RUN: llvm-objdump -d -r - | FileCheck -check-prefixes=ALL,O32 %s # RUN: llvm-objdump -d -r - | FileCheck -check-prefixes=ALL,O32 %s
# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi o32 %s | \ # RUN: llvm-mc -triple mips-unknown-unknown -target-abi o32 %s | \
# RUN: FileCheck -check-prefixes=ALL,ASM %s # RUN: FileCheck -check-prefixes=ALL,ASM,ASM-O32 %s
# RUN: llvm-mc -triple mips64-unknown-linux -target-abi n32 -filetype=obj -o - %s | \ # RUN: llvm-mc -triple mips64-unknown-linux -target-abi n32 -filetype=obj -o - %s | \
# RUN: llvm-objdump -d -r - | \ # RUN: llvm-objdump -d -r - | \
# RUN: FileCheck -check-prefixes=ALL,NXX,N32 %s # RUN: FileCheck -check-prefixes=ALL,NXX,N32 %s
# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi n32 %s | \ # RUN: llvm-mc -triple mips64-unknown-unknown -target-abi n32 %s | \
# RUN: FileCheck -check-prefixes=ALL,ASM %s # RUN: FileCheck -check-prefixes=ALL,ASM,ASM-N32 %s
# RUN: llvm-mc -triple mips64-unknown-linux %s -filetype=obj -o - | \ # RUN: llvm-mc -triple mips64-unknown-linux %s -filetype=obj -o - | \
# RUN: llvm-objdump -d -r - | \ # RUN: llvm-objdump -d -r - | \
# RUN: FileCheck -check-prefixes=ALL,NXX,N64 %s # RUN: FileCheck -check-prefixes=ALL,NXX,N64 %s
# RUN: llvm-mc -triple mips64-unknown-unknown %s | \ # RUN: llvm-mc -triple mips64-unknown-unknown %s | \
# RUN: FileCheck -check-prefixes=ALL,ASM %s # RUN: FileCheck -check-prefixes=ALL,ASM,ASM-N64 %s
.text .text
.option pic2 .option pic2
t1: t1:
.cpsetup $25, 8, __cerror .cpsetup $25, 8, __cerror
nop nop
.cpreturn .cpreturn
nop nop
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# N64-NEXT: {{^ *0+}}40: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 .text # N64-NEXT: {{^ *0+}}40: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 .text
# NXX-NEXT: addiu $gp, $gp, 0 # NXX-NEXT: addiu $gp, $gp, 0
# N32-NEXT: {{^ *0+}}3c: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE __gnu_local_gp # N32-NEXT: {{^ *0+}}3c: R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE __gnu_local_gp
# N64-NEXT: {{^ *0+}}44: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 .text # N64-NEXT: {{^ *0+}}44: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 .text
# N64-NEXT: daddu $gp, $gp, $25 # N64-NEXT: daddu $gp, $gp, $25
# NXX-NEXT: nop # NXX-NEXT: nop
# NXX-NEXT: sub $3, $3, $2 # NXX-NEXT: sub $3, $3, $2
# ASM: $tmp0: # ASM-O32: [[LABEL:\$tmp0]]:
# ASM-NEXT: .cpsetup $25, $2, $tmp0 # ASM-N32: [[LABEL:\.Ltmp0]]:
# ASM-N64: [[LABEL:\.Ltmp0]]:
# ASM-NEXT: .cpsetup $25, $2, [[LABEL]]
# Ensure we have at least one instruction between labels so that the labels # Ensure we have at least one instruction between labels so that the labels
# we're matching aren't removed. # we're matching aren't removed.
nop nop
# ALL-NEXT: nop # ALL-NEXT: nop
.option pic0 .option pic0
t4: t4:
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llvm/trunk/test/MC/Mips/expansion-jal-sym-pic.s

# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding |\ # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding |\
# RUN: FileCheck %s -check-prefixes=ALL,NORMAL,O32 # RUN: FileCheck %s -check-prefixes=ALL,NORMAL,O32
# RUN: llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 -show-encoding |\ # RUN: llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 -show-encoding |\
# RUN: FileCheck %s -check-prefixes=ALL,NORMAL,N32 # RUN: FileCheck %s -check-prefixes=ALL,NORMAL,N32
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 -show-encoding |\ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 -show-encoding |\
# RUN: FileCheck %s -check-prefixes=ALL,NORMAL,N64 # RUN: FileCheck %s -check-prefixes=ALL,NORMAL,N64
# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=micromips -show-encoding |\ # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=micromips -show-encoding |\
# RUN: FileCheck %s -check-prefixes=ALL,MICROMIPS,O32-MICROMIPS # RUN: FileCheck %s -check-prefixes=ALL,MICROMIPS,O32-MICROMIPS
# RUN: llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 -mattr=micromips -show-encoding |\ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 -mattr=micromips -show-encoding |\
# RUN: FileCheck %s -check-prefixes=ALL,MICROMIPS,N32-MICROMIPS # RUN: FileCheck %s -check-prefixes=ALL,MICROMIPS,N32-MICROMIPS
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 -mattr=micromips -show-encoding |\ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 -mattr=micromips -show-encoding |\
# RUN: FileCheck %s -check-prefixes=ALL,MICROMIPS,N64-MICROMIPS # RUN: FileCheck %s -check-prefixes=ALL,MICROMIPS,N64-MICROMIPS
.weak weak_label .weak weak_label
.text .text
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# O32: lw $25, %got($tmp0)($gp) # encoding: [0x8f,0x99,A,A] # O32: lw $25, %got($tmp0)($gp) # encoding: [0x8f,0x99,A,A]
# O32: # fixup A - offset: 0, value: %got($tmp0), kind: fixup_Mips_GOT # O32: # fixup A - offset: 0, value: %got($tmp0), kind: fixup_Mips_GOT
# O32: addiu $25, $25, %lo($tmp0) # encoding: [0x27,0x39,A,A] # O32: addiu $25, $25, %lo($tmp0) # encoding: [0x27,0x39,A,A]
# O32: # fixup A - offset: 0, value: %lo($tmp0), kind: fixup_Mips_LO16 # O32: # fixup A - offset: 0, value: %lo($tmp0), kind: fixup_Mips_LO16
# N32: lw $25, %got_disp($tmp0)($gp) # encoding: [0x8f,0x99,A,A] # N32: lw $25, %got_disp($tmp0)($gp) # encoding: [0x8f,0x99,A,A]
# N32: # fixup A - offset: 0, value: %got_disp($tmp0), kind: fixup_Mips_GOT_DISP # N32: # fixup A - offset: 0, value: %got_disp($tmp0), kind: fixup_Mips_GOT_DISP
# N64: ld $25, %got_disp($tmp0)($gp) # encoding: [0xdf,0x99,A,A] # N64: ld $25, %got_disp(.Ltmp0)($gp) # encoding: [0xdf,0x99,A,A]
# N64: # fixup A - offset: 0, value: %got_disp($tmp0), kind: fixup_Mips_GOT_DISP # N64: # fixup A - offset: 0, value: %got_disp(.Ltmp0), kind: fixup_Mips_GOT_DISP
# O32-MICROMIPS: lw $25, %got($tmp0)($gp) # encoding: [0xff,0x3c,A,A] # O32-MICROMIPS: lw $25, %got($tmp0)($gp) # encoding: [0xff,0x3c,A,A]
# O32-MICROMIPS: # fixup A - offset: 0, value: %got($tmp0), kind: fixup_MICROMIPS_GOT16 # O32-MICROMIPS: # fixup A - offset: 0, value: %got($tmp0), kind: fixup_MICROMIPS_GOT16
# O32-MICROMIPS: addiu $25, $25, %lo($tmp0) # encoding: [0x33,0x39,A,A] # O32-MICROMIPS: addiu $25, $25, %lo($tmp0) # encoding: [0x33,0x39,A,A]
# O32-MICROMIPS: # fixup A - offset: 0, value: %lo($tmp0), kind: fixup_MICROMIPS_LO16 # O32-MICROMIPS: # fixup A - offset: 0, value: %lo($tmp0), kind: fixup_MICROMIPS_LO16
# N32-MICROMIPS: lw $25, %got_disp($tmp0)($gp) # encoding: [0xff,0x3c,A,A] # N32-MICROMIPS: lw $25, %got_disp(.Ltmp0)($gp) # encoding: [0xff,0x3c,A,A]
# N32-MICROMIPS: # fixup A - offset: 0, value: %got_disp($tmp0), kind: fixup_MICROMIPS_GOT_DISP # N32-MICROMIPS: # fixup A - offset: 0, value: %got_disp(.Ltmp0), kind: fixup_MICROMIPS_GOT_DISP
# N64-MICROMIPS: ld $25, %got_disp($tmp0)($gp) # encoding: [0xdf,0x99,A,A] # N64-MICROMIPS: ld $25, %got_disp(.Ltmp0)($gp) # encoding: [0xdf,0x99,A,A]
# N64-MICROMIPS: # fixup A - offset: 0, value: %got_disp($tmp0), kind: fixup_MICROMIPS_GOT_DISP # N64-MICROMIPS: # fixup A - offset: 0, value: %got_disp(.Ltmp0), kind: fixup_MICROMIPS_GOT_DISP
# NORMAL: jalr $25 # encoding: [0x03,0x20,0xf8,0x09] # NORMAL: jalr $25 # encoding: [0x03,0x20,0xf8,0x09]
# MICROMIPS: jalr $ra, $25 # encoding: [0x03,0xf9,0x0f,0x3c] # MICROMIPS: jalr $ra, $25 # encoding: [0x03,0xf9,0x0f,0x3c]
# ALL: nop # encoding: [0x00,0x00,0x00,0x00] # ALL: nop # encoding: [0x00,0x00,0x00,0x00]

llvm/trunk/test/MC/Mips/macro-la.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \
# RUN: FileCheck %s # RUN: FileCheck %s --check-prefixes=CHECK,O32
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | \ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | \
# RUN: FileCheck %s # RUN: FileCheck %s --check-prefixes=CHECK,O32
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 -target-abi=n32 | \ # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 -target-abi=n32 | \
# RUN: FileCheck %s # RUN: FileCheck %s --check-prefixes=CHECK,N32
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 -target-abi=n32 | \ # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 -target-abi=n32 | \
# RUN: FileCheck %s # RUN: FileCheck %s --check-prefixes=CHECK,N32
# N64 should be acceptable too but we cannot convert la to dla yet. # N64 should be acceptable too but we cannot convert la to dla yet.
la $5, 0x00000001 # CHECK: addiu $5, $zero, 1 # encoding: [0x24,0x05,0x00,0x01] la $5, 0x00000001 # CHECK: addiu $5, $zero, 1 # encoding: [0x24,0x05,0x00,0x01]
la $5, 0x00000002 # CHECK: addiu $5, $zero, 2 # encoding: [0x24,0x05,0x00,0x02] la $5, 0x00000002 # CHECK: addiu $5, $zero, 2 # encoding: [0x24,0x05,0x00,0x02]
la $5, 0x00004000 # CHECK: addiu $5, $zero, 16384 # encoding: [0x24,0x05,0x40,0x00] la $5, 0x00004000 # CHECK: addiu $5, $zero, 16384 # encoding: [0x24,0x05,0x40,0x00]
la $5, 0x00008000 # CHECK: ori $5, $zero, 32768 # encoding: [0x34,0x05,0x80,0x00] la $5, 0x00008000 # CHECK: ori $5, $zero, 32768 # encoding: [0x34,0x05,0x80,0x00]
la $5, 0xffffffff # CHECK: addiu $5, $zero, -1 # encoding: [0x24,0x05,0xff,0xff] la $5, 0xffffffff # CHECK: addiu $5, $zero, -1 # encoding: [0x24,0x05,0xff,0xff]
▲ Show 20 Lines • Show All 250 Lines • ▼ Show 20 Linesla $5, symbol+8($6) # CHECK: lui $5, %hi(symbol+8) # encoding: [0x3c,0x05,A,A]
# CHECK: addiu $5, $5, %lo(symbol+8) # encoding: [0x24,0xa5,A,A] # CHECK: addiu $5, $5, %lo(symbol+8) # encoding: [0x24,0xa5,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(symbol+8), kind: fixup_Mips_LO16 # CHECK: # fixup A - offset: 0, value: %lo(symbol+8), kind: fixup_Mips_LO16
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21] # CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
la $6, symbol+8($6) # CHECK: lui $1, %hi(symbol+8) # encoding: [0x3c,0x01,A,A] la $6, symbol+8($6) # CHECK: lui $1, %hi(symbol+8) # encoding: [0x3c,0x01,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(symbol+8), kind: fixup_Mips_HI16 # CHECK: # fixup A - offset: 0, value: %hi(symbol+8), kind: fixup_Mips_HI16
# CHECK: addiu $1, $1, %lo(symbol+8) # encoding: [0x24,0x21,A,A] # CHECK: addiu $1, $1, %lo(symbol+8) # encoding: [0x24,0x21,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(symbol+8), kind: fixup_Mips_LO16 # CHECK: # fixup A - offset: 0, value: %lo(symbol+8), kind: fixup_Mips_LO16
# CHECK: addu $6, $1, $6 # encoding: [0x00,0x26,0x30,0x21] # CHECK: addu $6, $1, $6 # encoding: [0x00,0x26,0x30,0x21]
la $5, 1f # CHECK: lui $5, %hi($tmp0) # encoding: [0x3c,0x05,A,A] la $5, 1f # O32: lui $5, %hi($tmp0) # encoding: [0x3c,0x05,A,A]
# CHECK: # fixup A - offset: 0, value: %hi($tmp0), kind: fixup_Mips_HI16 # O32: # fixup A - offset: 0, value: %hi($tmp0), kind: fixup_Mips_HI16
# CHECK: addiu $5, $5, %lo($tmp0) # encoding: [0x24,0xa5,A,A] # O32: addiu $5, $5, %lo($tmp0) # encoding: [0x24,0xa5,A,A]
# CHECK: # fixup A - offset: 0, value: %lo($tmp0), kind: fixup_Mips_LO16 # O32: # fixup A - offset: 0, value: %lo($tmp0), kind: fixup_Mips_LO16
# N32: lui $5, %hi(.Ltmp0) # encoding: [0x3c,0x05,A,A]
# N32: # fixup A - offset: 0, value: %hi(.Ltmp0), kind: fixup_Mips_HI16
# N32: addiu $5, $5, %lo(.Ltmp0) # encoding: [0x24,0xa5,A,A]
# N32: # fixup A - offset: 0, value: %lo(.Ltmp0), kind: fixup_Mips_LO16
1: 1:

llvm/trunk/test/MC/Mips/mips3/valid.s

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Linesa:
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b] jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ld $sp,-28645($s1) ld $sp,-28645($s1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
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llvm/trunk/test/MC/Mips/mips4/valid.s

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Linesa:
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b] jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ld $sp,-28645($s1) ld $sp,-28645($s1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
▲ Show 20 Lines • Show All 178 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips5/valid.s

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Linesa:
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b] jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ld $sp,-28645($s1) ld $sp,-28645($s1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
▲ Show 20 Lines • Show All 180 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64/valid.s

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Linesa:
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b] jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
lb $24,-14515($10) lb $24,-14515($10)
lbu $8,30195($v1) lbu $8,30195($v1)
ld $sp,-28645($s1) ld $sp,-28645($s1)
ldc1 $f11,16391($s0) ldc1 $f11,16391($s0)
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llvm/trunk/test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Linesa:
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b] jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
lb $24,-14515($10) lb $24,-14515($10)
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llvm/trunk/test/MC/Mips/mips64r3/valid.s

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Linesa:
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret eret
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b] jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
lb $24,-14515($10) lb $24,-14515($10)
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llvm/trunk/test/MC/Mips/mips64r5/valid.s

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Linesa:
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret eret
eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58] eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b] jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
lb $24,-14515($10) lb $24,-14515($10)
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