[AMDGPU] Emit got relocs for linkonce[_odr] constant symbols

[• tstellarAMD]

lib/Target/AMDGPU/SIISelLowering.cpp

1524–1525

What we do currently is to emit read-only data to the .text section, and then have the compiler use fixups to resolve the offsets. So, we don't really need to be emitting relocations or these type of symbols at all.

However, it's really not correct to emit read-only data to the .text section, so I think we should fix this. We need to update the callback in AMDGPUTargetObjectFile.cpp to emit constant to the correct section (but only for isAmdHsaOS()), and then here we shouldn't be special casing linkonce/linkonce_odr we should be emitting GOTs for all constant address space variables that are not DSOLocal.

[kzhuravl]

This workaround is not needed any more

lib/Target/AMDGPU/SIISelLowering.cpp

1524–1525

I agree, this was a temp workaround. I will send a separate patch for emitting read-only data to the right section

lib/Target/AMDGPU/SIISelLowering.cpp

DiagnosticInfoUnsupported InvalidAddrSpaceCast(
     *MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
   DAG.getContext()->diagnose(InvalidAddrSpaceCast);
 
   return DAG.getUNDEF(ASC->getValueType(0));
 }
 
 static bool shouldEmitGOTReloc(const GlobalValue *GV,
                                const TargetMachine &TM) {
-  return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
+  return (GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
+            GV->hasLinkOnceLinkage() || GV->hasLinkOnceODRLinkage()) &&
          !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
 }
 
 bool
 SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
   // We can fold offsets for anything that doesn't require a GOT relocation.
   return GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
          !shouldEmitGOTReloc(GA->getGlobal(), getTargetMachine());

test/CodeGen/AMDGPU/global-variable-relocs.ll

 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s
 
 @private = private addrspace(1) global [256 x i32] zeroinitializer
 @internal = internal addrspace(1) global [256 x i32] zeroinitializer
 @available_externally = available_externally addrspace(1) global [256 x i32] zeroinitializer
 @linkonce = linkonce addrspace(1) global [256 x i32] zeroinitializer
+@linkonce_const = linkonce addrspace(2) constant [256 x i32] zeroinitializer
 @weak= weak addrspace(1) global [256 x i32] zeroinitializer
 @common = common addrspace(1) global [256 x i32] zeroinitializer
 @extern_weak = extern_weak addrspace(1) global [256 x i32]
 @linkonce_odr = linkonce_odr addrspace(1) global [256 x i32] zeroinitializer
+@linkonce_odr_const = linkonce_odr addrspace(2) constant [256 x i32] zeroinitializer
 @weak_odr = weak_odr addrspace(1) global [256 x i32] zeroinitializer
 @external = external addrspace(1) global [256 x i32]
 @external_w_init = addrspace(1) global [256 x i32] zeroinitializer
 
 ; CHECK-LABEL: private_test:
 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
 ; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], private+8
 ; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], 0

 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
 define void @linkonce_test(i32 addrspace(1)* %out) {
   %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @linkonce, i32 0, i32 1
   %val = load i32, i32 addrspace(1)* %ptr
   store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
+; CHECK-LABEL: linkonce_const_test:
+; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce_const@GOTPCREL+4
+; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0
+; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0
+define void @linkonce_const_test(i32 addrspace(1)* %out) {
+entry:
+  %0 = load i32, i32 addrspace(1)* %out, align 4
+  %1 = sext i32 %0 to i64
+  %arrayidx1 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(2)* @linkonce_const, i64 0, i64 %1
+  %2 = load i32, i32 addrspace(2)* %arrayidx1, align 4
+  store i32 %2, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
 ; CHECK-LABEL: weak_test:
 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak@GOTPCREL+4
 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0
 ; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0
 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
 ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]

 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
 define void @linkonce_odr_test(i32 addrspace(1)* %out) {
   %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @linkonce_odr, i32 0, i32 1
   %val = load i32, i32 addrspace(1)* %ptr
   store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
+; CHECK-LABEL: linkonce_odr_const_test:
+; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce_odr_const@GOTPCREL+4
+; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0
+; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0
+define void @linkonce_odr_const_test(i32 addrspace(1)* %out) {
+entry:
+  %0 = load i32, i32 addrspace(1)* %out, align 4
+  %1 = sext i32 %0 to i64
+  %arrayidx1 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(2)* @linkonce_odr_const, i64 0, i64 %1
+  %2 = load i32, i32 addrspace(2)* %arrayidx1, align 4
+  store i32 %2, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
 ; CHECK-LABEL: weak_odr_test:
 ; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
 ; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak_odr@GOTPCREL+4
 ; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0
 ; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0
 ; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4
 ; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0
 ; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]]