AMDGPU: Remove brev intrinsic

[• tstellarAMD]

LGTM.

[arsenm]

r275620

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

case AMDGPUIntrinsic::AMDGPU_bfe_i32:
                          Op.getOperand(2),
                          Op.getOperand(3));
 
     case AMDGPUIntrinsic::AMDGPU_bfe_u32:
       return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
                          Op.getOperand(1),
                          Op.getOperand(2),
                          Op.getOperand(3));
-
-    case AMDGPUIntrinsic::AMDGPU_brev: // Legacy name
-      return DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(1));
   }
 }
 
 /// \brief Generate Min/Max node
 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(const SDLoc &DL, EVT VT,
                                                    SDValue LHS, SDValue RHS,
                                                    SDValue True, SDValue False,
                                                    SDValue CC,

lib/Target/AMDGPU/AMDGPUIntrinsics.td

let TargetPrefix = "AMDGPU", isTarget = 1 in {
   def int_AMDGPU_bfe_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
   def int_AMDGPU_bfe_u32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 
   // Deprecated in favor of llvm.amdgcn.rsq
   def int_AMDGPU_rsq : Intrinsic<
     [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
   >;
 
-  // Deprecated in favor of llvm.bitreverse
-  def int_AMDGPU_brev : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
-
   // Deprecated in favor of llvm.amdgcn.s.barrier
   def int_AMDGPU_barrier_local  : Intrinsic<[], [], [IntrConvergent]>;
   def int_AMDGPU_barrier_global : Intrinsic<[], [], [IntrConvergent]>;
 
   // Deprecated in favor of llvm.amdgcn.read.workdim
   def int_AMDGPU_read_workdim : Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
 }
 
 include "SIIntrinsics.td"

test/CodeGen/AMDGPU/bitreverse.ll

 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
 
 declare i16 @llvm.bitreverse.i16(i16) #1
 declare i32 @llvm.bitreverse.i32(i32) #1
 declare i64 @llvm.bitreverse.i64(i64) #1
 
 declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>) #1
 declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1
 
 declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1
 declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1
 
-declare i32 @llvm.AMDGPU.brev(i32) #1
-
 ; FUNC-LABEL: {{^}}s_brev_i16:
 ; SI: s_brev_b32
 define void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 {
   %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
   store i16 %brev, i16 addrspace(1)* %out
   ret void
 }
 

 ; FUNC-LABEL: {{^}}v_brev_v2i64:
 define void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %valptr) #0 {
   %val = load <2 x i64>, <2 x i64> addrspace(1)* %valptr
   %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
   store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
   ret void
 }
 
-; FUNC-LABEL: {{^}}legacy_s_brev_i32:
-; SI: s_brev_b32
-define void @legacy_s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
-  %brev = call i32 @llvm.AMDGPU.brev(i32 %val) #1
-  store i32 %brev, i32 addrspace(1)* %out
-  ret void
-}
-
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }