AMDGPU: Remove legacy rsq.clamped intrinsic

[arsenm]

Summary

Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining.

Also fix mismatch with non-IEEE rsq selecting to IEEE rsq.

[• tstellarAMD]

LGTM.

[arsenm]

r275617

include/llvm/IR/IntrinsicsAMDGPU.td

 
 def int_r600_rat_store_typed :
   // 1st parameter: Data
   // 2nd parameter: Index
   // 3rd parameter: Constant RAT ID
   Intrinsic<[], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], []>,
   GCCBuiltin<"__builtin_r600_rat_store_typed">;
 
-def int_r600_rsq : Intrinsic<
+def int_r600_recipsqrt_ieee :  Intrinsic<
   [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
 >;
 
+def int_r600_recipsqrt_clamped : Intrinsic<
+  [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
+>;
 
 } // End TargetPrefix = "r600"
 
 // FIXME: These should be renamed/moved to r600
 let TargetPrefix = "AMDGPU" in {
 def int_AMDGPU_ldexp : Intrinsic<
   [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]
 >;

lib/Target/AMDGPU/AMDGPUIntrinsics.td

let TargetPrefix = "AMDGPU", isTarget = 1 in {
 
   // Deprecated in favor of separate int_amdgcn_cube* intrinsics.
   def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 
   // Deprecated in favor of expanded bit operations
   def int_AMDGPU_bfe_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
   def int_AMDGPU_bfe_u32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 
-  def int_AMDGPU_rsq_clamped :  Intrinsic<
-    [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
-  >;
-
   // Deprecated in favor of llvm.amdgcn.rsq
   def int_AMDGPU_rsq : Intrinsic<
     [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
   >;
 
   // Deprecated in favor of llvm.bitreverse
   def int_AMDGPU_brev : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 

lib/Target/AMDGPU/R600ISelLowering.cpp

case Intrinsic::r600_read_tidig_x:
                                   AMDGPU::T0_X, VT);
     case Intrinsic::r600_read_tidig_y:
       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
                                   AMDGPU::T0_Y, VT);
     case Intrinsic::r600_read_tidig_z:
       return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
                                   AMDGPU::T0_Z, VT);
 
-    // FIXME: Should be renamed to r600 prefix
-    case AMDGPUIntrinsic::AMDGPU_rsq_clamped:
-      return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
+    case Intrinsic::r600_recipsqrt_ieee:
+      return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
 
-    case Intrinsic::r600_rsq:
-    case AMDGPUIntrinsic::AMDGPU_rsq: // Legacy name
-      // XXX - I'm assuming SI's RSQ_LEGACY matches R600's behavior.
-      return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
+    case Intrinsic::r600_recipsqrt_clamped:
+      return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
     }
+
     // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
     break;
   }
   } // end switch(Op.getOpcode())
   return SDValue();
 }
 
 void R600TargetLowering::ReplaceNodeResults(SDNode *N,

lib/Target/AMDGPU/R600Instructions.td

 // Clamped to maximum.
 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
   inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamp
 > {
   let Itinerary = TransALU;
 }
 
 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
-  inst, "RECIPSQRT_IEEE", AMDGPUrsq_legacy
-> {
+  inst, "RECIPSQRT_IEEE", AMDGPUrsq> {
   let Itinerary = TransALU;
 }
 
 // TODO: There is also RECIPSQRT_FF which clamps to zero.
 
 class SIN_Common <bits<11> inst> : R600_1OP <
   inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
   let Trig = 1;

lib/Target/AMDGPU/SIISelLowering.cpp

SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   case AMDGPUIntrinsic::AMDGPU_rsq: // Legacy name
     return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
   case Intrinsic::amdgcn_rsq_legacy: {
     if (Subtarget->getGeneration() >= SISubtarget::VOLCANIC_ISLANDS)
       return emitRemovedIntrinsicError(DAG, DL, VT);
 
     return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
   }
-  case Intrinsic::amdgcn_rsq_clamp:
-  case AMDGPUIntrinsic::AMDGPU_rsq_clamped: { // Legacy name
+  case Intrinsic::amdgcn_rsq_clamp: {
     if (Subtarget->getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
       return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
 
     Type *Type = VT.getTypeForEVT(*DAG.getContext());
     APFloat Max = APFloat::getLargest(Type->getFltSemantics());
     APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
 
     SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));

test/CodeGen/AMDGPU/big_alu.ll

IF137:                                            ; preds = %main_body
   %tmp83 = insertelement <4 x float> %tmp82, float %tmp31, i32 1
   %tmp84 = insertelement <4 x float> %tmp83, float %tmp32, i32 2
   %tmp85 = insertelement <4 x float> %tmp84, float 0.000000e+00, i32 3
   %tmp86 = insertelement <4 x float> undef, float %tmp30, i32 0
   %tmp87 = insertelement <4 x float> %tmp86, float %tmp31, i32 1
   %tmp88 = insertelement <4 x float> %tmp87, float %tmp32, i32 2
   %tmp89 = insertelement <4 x float> %tmp88, float 0.000000e+00, i32 3
   %tmp90 = call float @llvm.r600.dot4(<4 x float> %tmp85, <4 x float> %tmp89)
-  %tmp91 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp90)
+  %tmp91 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp90)
   %tmp92 = fmul float %tmp30, %tmp91
   %tmp93 = fmul float %tmp31, %tmp91
   %tmp94 = fmul float %tmp32, %tmp91
   %tmp95 = insertelement <4 x float> undef, float %tmp92, i32 0
   %tmp96 = insertelement <4 x float> %tmp95, float %tmp93, i32 1
   %tmp97 = insertelement <4 x float> %tmp96, float %tmp94, i32 2
   %tmp98 = insertelement <4 x float> %tmp97, float 0.000000e+00, i32 3
   %tmp99 = insertelement <4 x float> undef, float %tmp37, i32 0
ENDIF136:                                         ; preds = %ENDIF154, %main_body
   %tmp176 = extractelement <4 x float> %tmp175, i32 0
   %tmp177 = extractelement <4 x float> %tmp175, i32 1
   %tmp178 = extractelement <4 x float> %tmp175, i32 2
   %tmp179 = extractelement <4 x float> %tmp175, i32 3
   %tmp180 = fmul float %tmp178, 3.000000e+03
   %tmp181 = fadd float %tmp180, %tmp28
   %tmp182 = fdiv float 1.000000e+00, %tmp33
   %tmp183 = fmul float %tmp32, %tmp182
-  %tmp184 = call float @fabs(float %tmp183)
+  %tmp184 = call float @llvm.fabs.f32(float %tmp183)
   %tmp185 = fmul float %tmp176, 0x3FD99999A0000000
   %tmp186 = fadd float %tmp185, 0x3FAEB851E0000000
   %tmp187 = fmul float %tmp177, 0x3FE3333340000000
   %tmp188 = fadd float %tmp187, %tmp186
   %tmp189 = fmul float %tmp178, 2.000000e+00
   %tmp190 = fadd float %tmp189, %tmp188
   %tmp191 = fmul float %tmp179, 4.000000e+00
   %tmp192 = fadd float %tmp191, %tmp190
ENDIF136:                                         ; preds = %ENDIF154, %main_body
   %tmp324 = insertelement <4 x float> %tmp323, float %tmp320, i32 1
   %tmp325 = insertelement <4 x float> %tmp324, float %tmp322, i32 2
   %tmp326 = insertelement <4 x float> %tmp325, float 0.000000e+00, i32 3
   %tmp327 = insertelement <4 x float> undef, float %tmp318, i32 0
   %tmp328 = insertelement <4 x float> %tmp327, float %tmp320, i32 1
   %tmp329 = insertelement <4 x float> %tmp328, float %tmp322, i32 2
   %tmp330 = insertelement <4 x float> %tmp329, float 0.000000e+00, i32 3
   %tmp331 = call float @llvm.r600.dot4(<4 x float> %tmp326, <4 x float> %tmp330)
-  %tmp332 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp331)
+  %tmp332 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp331)
   %tmp333 = fmul float %tmp318, %tmp332
   %tmp334 = fmul float %tmp320, %tmp332
   %tmp335 = fmul float %tmp322, %tmp332
   %tmp336 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
   %tmp337 = extractelement <4 x float> %tmp336, i32 0
   %tmp338 = fsub float -0.000000e+00, %tmp337
   %tmp339 = fadd float 1.000000e+00, %tmp338
   %tmp340 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
ENDIF136:                                         ; preds = %ENDIF154, %main_body
   %tmp357 = insertelement <4 x float> %tmp356, float %tmp44, i32 1
   %tmp358 = insertelement <4 x float> %tmp357, float %tmp45, i32 2
   %tmp359 = insertelement <4 x float> %tmp358, float 0.000000e+00, i32 3
   %tmp360 = insertelement <4 x float> undef, float %tmp43, i32 0
   %tmp361 = insertelement <4 x float> %tmp360, float %tmp44, i32 1
   %tmp362 = insertelement <4 x float> %tmp361, float %tmp45, i32 2
   %tmp363 = insertelement <4 x float> %tmp362, float 0.000000e+00, i32 3
   %tmp364 = call float @llvm.r600.dot4(<4 x float> %tmp359, <4 x float> %tmp363)
-  %tmp365 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp364)
+  %tmp365 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp364)
   %tmp366 = fmul float %tmp45, %tmp365
-  %tmp367 = call float @fabs(float %tmp366)
+  %tmp367 = call float @llvm.fabs.f32(float %tmp366)
   %tmp368 = fmul float %tmp178, 0x3FECCCCCC0000000
   %tmp369 = fadd float %tmp368, %tmp367
   %tmp370 = fadd float %tmp369, 0xBFEFAE1480000000
   %tmp371 = fmul float %tmp370, 0xC023FFFFC0000000
   %tmp372 = call float @llvm.AMDGPU.clamp.f32(float %tmp371, float 0.000000e+00, float 1.000000e+00)
   %tmp373 = fsub float -0.000000e+00, %tmp339
   %tmp374 = fadd float %result.i, %tmp373
   %tmp375 = fadd float %tmp374, 0x3FBEB851E0000000
   %tmp376 = fsub float -0.000000e+00, %tmp343
   %tmp377 = fadd float %result.i, %tmp376
   %tmp378 = fadd float %tmp377, 0xBFE0A3D700000000
   %tmp379 = fsub float -0.000000e+00, %result.i
   %tmp380 = fsub float -0.000000e+00, %tmp347
   %tmp381 = fadd float %tmp379, %tmp380
   %tmp382 = insertelement <4 x float> undef, float %tmp43, i32 0
   %tmp383 = insertelement <4 x float> %tmp382, float %tmp44, i32 1
   %tmp384 = insertelement <4 x float> %tmp383, float %tmp45, i32 2
   %tmp385 = insertelement <4 x float> %tmp384, float 0.000000e+00, i32 3
   %tmp386 = insertelement <4 x float> undef, float %tmp43, i32 0
   %tmp387 = insertelement <4 x float> %tmp386, float %tmp44, i32 1
   %tmp388 = insertelement <4 x float> %tmp387, float %tmp45, i32 2
   %tmp389 = insertelement <4 x float> %tmp388, float 0.000000e+00, i32 3
   %tmp390 = call float @llvm.r600.dot4(<4 x float> %tmp385, <4 x float> %tmp389)
-  %tmp391 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp390)
+  %tmp391 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp390)
   %tmp392 = fmul float %tmp45, %tmp391
-  %tmp393 = call float @fabs(float %tmp392)
+  %tmp393 = call float @llvm.fabs.f32(float %tmp392)
   %tmp394 = fmul float %tmp178, 0x3FF51EB860000000
   %tmp395 = fadd float %tmp394, %tmp393
   %tmp396 = fadd float %tmp395, 0xBFEFAE1480000000
   %tmp397 = fmul float %tmp396, 0xC0490001A0000000
   %tmp398 = call float @llvm.AMDGPU.clamp.f32(float %tmp397, float 0.000000e+00, float 1.000000e+00)
   %tmp399 = fmul float 2.000000e+00, %tmp372
   %tmp400 = fsub float -0.000000e+00, %tmp399
   %tmp401 = fadd float 3.000000e+00, %tmp400
IF179:                                            ; preds = %ENDIF175
   %tmp870 = insertelement <4 x float> %tmp869, float %tmp44, i32 1
   %tmp871 = insertelement <4 x float> %tmp870, float %tmp45, i32 2
   %tmp872 = insertelement <4 x float> %tmp871, float 0.000000e+00, i32 3
   %tmp873 = insertelement <4 x float> undef, float %tmp43, i32 0
   %tmp874 = insertelement <4 x float> %tmp873, float %tmp44, i32 1
   %tmp875 = insertelement <4 x float> %tmp874, float %tmp45, i32 2
   %tmp876 = insertelement <4 x float> %tmp875, float 0.000000e+00, i32 3
   %tmp877 = call float @llvm.r600.dot4(<4 x float> %tmp872, <4 x float> %tmp876)
-  %tmp878 = call float @llvm.AMDGPU.rsq.clamped.f32(float %tmp877)
+  %tmp878 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp877)
   %tmp879 = fmul float %tmp45, %tmp878
-  %tmp880 = call float @fabs(float %tmp879)
+  %tmp880 = call float @llvm.fabs.f32(float %tmp879)
   %tmp881 = fmul float %tmp178, 0x3FECCCCCC0000000
   %tmp882 = fadd float %tmp881, %tmp880
   %tmp883 = fadd float %tmp882, 0xBFEFAE1480000000
   %tmp884 = fmul float %tmp883, 0xC043FFFE20000000
   %tmp885 = call float @llvm.AMDGPU.clamp.f32(float %tmp884, float 0.000000e+00, float 1.000000e+00)
   %tmp886 = fmul float 2.000000e+00, %tmp885
   %tmp887 = fsub float -0.000000e+00, %tmp886
   %tmp888 = fadd float 3.000000e+00, %tmp887
ENDIF178:                                         ; preds = %IF179, %ENDIF175
   call void @llvm.R600.store.swizzle(<4 x float> %tmp956, i32 0, i32 0)
   ret void
 }
 
 ; Function Attrs: nounwind readnone
 declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #0
 
 ; Function Attrs: nounwind readnone
-declare float @llvm.AMDGPU.rsq.clamped.f32(float) #0
+declare float @llvm.r600.recipsqrt.clamped.f32(float) #0
 
 ; Function Attrs: nounwind readonly
-declare float @fabs(float) #1
+declare float @llvm.fabs.f32(float) #1
 
 ; Function Attrs: nounwind readnone
 declare float @llvm.exp2.f32(float) #0
 
 ; Function Attrs: nounwind readnone
 declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
 
 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
 
 ; Function Attrs: nounwind readnone
 declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind readonly }

test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.f64.ll

-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
-
-declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone
-
-; FUNC-LABEL: {{^}}rsq_clamped_f64:
-; SI: v_rsq_clamp_f64_e32
-
-; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}]
-; TODO: this constant should be folded:
-; VI-DAG: s_mov_b32 s[[LOW1:[0-9+]]], -1
-; VI-DAG: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
-; VI-DAG: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
-; VI-DAG: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
-; VI-DAG: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW1]]:[[HIGH2]]]
-
-define void @rsq_clamped_f64(double addrspace(1)* %out, double %src) nounwind {
-  %rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone
-  store double %rsq_clamped, double addrspace(1)* %out, align 8
-  ret void
-}

test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.ll

-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-; FIXME: Uses of this should be moved to llvm.amdgcn.rsq.clamped, and
-; an r600 variant added.
-
-declare float @llvm.AMDGPU.rsq.clamped.f32(float) nounwind readnone
-
-; FUNC-LABEL: {{^}}rsq_clamped_f32:
-; SI: v_rsq_clamp_f32_e32
-
-; VI-DAG: v_rsq_f32_e32 [[RSQ:v[0-9]+]], {{s[0-9]+}}
-; VI-DAG: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]]
-; TODO: this constant should be folded:
-; VI-DAG: v_mov_b32_e32 [[MINFLT:v[0-9]+]], 0xff7fffff
-; VI: v_max_f32_e32 {{v[0-9]+}}, [[MIN]], [[MINFLT]]
-
-; EG: RECIPSQRT_CLAMPED
-
-define void @rsq_clamped_f32(float addrspace(1)* %out, float %src) nounwind {
-  %rsq_clamped = call float @llvm.AMDGPU.rsq.clamped.f32(float %src) nounwind readnone
-  store float %rsq_clamped, float addrspace(1)* %out, align 4
-  ret void
-}

test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll

-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-
-declare float @llvm.AMDGPU.rsq.f32(float) nounwind readnone
-
-; FUNC-LABEL: {{^}}rsq_f32:
-; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
-; EG: RECIPSQRT_IEEE
-define void @rsq_f32(float addrspace(1)* %out, float %src) nounwind {
-  %rsq = call float @llvm.AMDGPU.rsq.f32(float %src) nounwind readnone
-  store float %rsq, float addrspace(1)* %out, align 4
-  ret void
-}
-
-; TODO: Really these should be constant folded
-; FUNC-LABEL: {{^}}rsq_f32_constant_4.0
-; SI: v_rsq_f32_e32 {{v[0-9]+}}, 4.0
-; EG: RECIPSQRT_IEEE
-define void @rsq_f32_constant_4.0(float addrspace(1)* %out) nounwind {
-  %rsq = call float @llvm.AMDGPU.rsq.f32(float 4.0) nounwind readnone
-  store float %rsq, float addrspace(1)* %out, align 4
-  ret void
-}
-
-; FUNC-LABEL: {{^}}rsq_f32_constant_100.0
-; SI: v_rsq_f32_e32 {{v[0-9]+}}, 0x42c80000
-; EG: RECIPSQRT_IEEE
-define void @rsq_f32_constant_100.0(float addrspace(1)* %out) nounwind {
-  %rsq = call float @llvm.AMDGPU.rsq.f32(float 100.0) nounwind readnone
-  store float %rsq, float addrspace(1)* %out, align 4
-  ret void
-}

test/CodeGen/AMDGPU/llvm.r600.recipsqrt.clamped.ll

+; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
+
+declare float @llvm.r600.recipsqrt.clamped.f32(float) nounwind readnone
+
+; EG-LABEL: {{^}}rsq_clamped_f32:
+; EG: RECIPSQRT_CLAMPED
+define void @rsq_clamped_f32(float addrspace(1)* %out, float %src) nounwind {
+  %rsq_clamped = call float @llvm.r600.recipsqrt.clamped.f32(float %src)
+  store float %rsq_clamped, float addrspace(1)* %out, align 4
+  ret void
+}

test/CodeGen/AMDGPU/llvm.r600.recipsqrt.ieee.ll

+; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
+
+declare float @llvm.r600.recipsqrt.ieee.f32(float) nounwind readnone
+
+; EG-LABEL: {{^}}recipsqrt.ieee_f32:
+; EG: RECIPSQRT_IEEE
+define void @recipsqrt.ieee_f32(float addrspace(1)* %out, float %src) nounwind {
+  %recipsqrt.ieee = call float @llvm.r600.recipsqrt.ieee.f32(float %src) nounwind readnone
+  store float %recipsqrt.ieee, float addrspace(1)* %out, align 4
+  ret void
+}
+
+; TODO: Really these should be constant folded
+; EG-LABEL: {{^}}recipsqrt.ieee_f32_constant_4.0
+; EG: RECIPSQRT_IEEE
+define void @recipsqrt.ieee_f32_constant_4.0(float addrspace(1)* %out) nounwind {
+  %recipsqrt.ieee = call float @llvm.r600.recipsqrt.ieee.f32(float 4.0) nounwind readnone
+  store float %recipsqrt.ieee, float addrspace(1)* %out, align 4
+  ret void
+}
+
+; EG-LABEL: {{^}}recipsqrt.ieee_f32_constant_100.0
+; EG: RECIPSQRT_IEEE
+define void @recipsqrt.ieee_f32_constant_100.0(float addrspace(1)* %out) nounwind {
+  %recipsqrt.ieee = call float @llvm.r600.recipsqrt.ieee.f32(float 100.0) nounwind readnone
+  store float %recipsqrt.ieee, float addrspace(1)* %out, align 4
+  ret void
+}

test/CodeGen/AMDGPU/pv.ll

main_body:
   %89 = insertelement <4 x float> %88, float %5, i32 1
   %90 = insertelement <4 x float> %89, float %6, i32 2
   %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 3
   %92 = insertelement <4 x float> undef, float %4, i32 0
   %93 = insertelement <4 x float> %92, float %5, i32 1
   %94 = insertelement <4 x float> %93, float %6, i32 2
   %95 = insertelement <4 x float> %94, float 0.000000e+00, i32 3
   %96 = call float @llvm.r600.dot4(<4 x float> %91, <4 x float> %95)
-  %97 = call float @fabs(float %96)
-  %98 = call float @llvm.AMDGPU.rsq.clamped.f32(float %97)
+  %97 = call float @llvm.fabs.f32(float %96)
+  %98 = call float @llvm.r600.recipsqrt.clamped.f32(float %97)
   %99 = fmul float %4, %98
   %100 = fmul float %5, %98
   %101 = fmul float %6, %98
   %102 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
   %103 = extractelement <4 x float> %102, i32 0
   %104 = fmul float %103, %8
   %105 = fadd float %104, %20
   %106 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
main_body:
   call void @llvm.R600.store.swizzle(<4 x float> %207, i32 0, i32 2)
   ret void
 }
 
 ; Function Attrs: readnone
 declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1
 
 ; Function Attrs: readonly
-declare float @fabs(float) #2
+declare float @llvm.fabs.f32(float) #1
 
 ; Function Attrs: readnone
-declare float @llvm.AMDGPU.rsq.clamped.f32(float) #1
+declare float @llvm.r600.recipsqrt.clamped.f32(float) #1
 
 ; Function Attrs: readnone
 declare float @llvm.AMDGPU.clamp.f32(float, float, float) #1
 
 ; Function Attrs: nounwind readonly
-declare float @llvm.pow.f32(float, float) #3
+declare float @llvm.pow.f32(float, float) #2
 
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) #3
 
-attributes #1 = { readnone }
-attributes #2 = { readonly }
-attributes #3 = { nounwind readonly }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind readonly }
+attributes #3 = { nounwind }