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Differential D22068

[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
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Authored by jlebar on Jul 6 2016, 1:51 PM.

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tra
Commits
rG6f9d01bbd525: [NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
rL274674: [NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.

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rL LLVM

Event Timeline

jlebar updated this revision to Diff 62958.Jul 6 2016, 1:51 PM
jlebar retitled this revision from to [NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM..
jlebar updated this object.
jlebar added a reviewer: tra.
jlebar added a subscriber: llvm-commits.
Herald added a subscriber: jholewinski. · View Herald TranscriptJul 6 2016, 1:51 PM
tra accepted this revision.Jul 6 2016, 2:06 PM
tra edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Jul 6 2016, 2:06 PM
Closed by commit rL274674: [NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM. (authored by jlebar). · Explain WhyJul 6 2016, 2:13 PM
This revision was automatically updated to reflect the committed changes.
jlebar mentioned this in D21778: [CUDA] Add support for CUDA 8 and sm_60-62..Jul 6 2016, 2:16 PM
jlebar added a child revision: D21778: [CUDA] Add support for CUDA 8 and sm_60-62..

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
NVPTX/
14 lines
test/
CodeGen/
NVPTX/
5 lines
5 lines
5 lines

Diff 62965

llvm/trunk/lib/Target/NVPTX/NVPTX.td

Show All 38 Lines
def SM37 : SubtargetFeature<"sm_37", "SmVersion", "37", def SM37 : SubtargetFeature<"sm_37", "SmVersion", "37",
"Target SM 3.7">; "Target SM 3.7">;
def SM50 : SubtargetFeature<"sm_50", "SmVersion", "50", def SM50 : SubtargetFeature<"sm_50", "SmVersion", "50",
"Target SM 5.0">; "Target SM 5.0">;
def SM52 : SubtargetFeature<"sm_52", "SmVersion", "52", def SM52 : SubtargetFeature<"sm_52", "SmVersion", "52",
"Target SM 5.2">; "Target SM 5.2">;
def SM53 : SubtargetFeature<"sm_53", "SmVersion", "53", def SM53 : SubtargetFeature<"sm_53", "SmVersion", "53",
"Target SM 5.3">; "Target SM 5.3">;
def SM60 : SubtargetFeature<"sm_60", "SmVersion", "60",
"Target SM 6.0">;
def SM61 : SubtargetFeature<"sm_61", "SmVersion", "61",
"Target SM 6.1">;
def SM62 : SubtargetFeature<"sm_62", "SmVersion", "62",
"Target SM 6.2">;
// PTX Versions // PTX Versions
def PTX32 : SubtargetFeature<"ptx32", "PTXVersion", "32", def PTX32 : SubtargetFeature<"ptx32", "PTXVersion", "32",
"Use PTX version 3.2">; "Use PTX version 3.2">;
def PTX40 : SubtargetFeature<"ptx40", "PTXVersion", "40", def PTX40 : SubtargetFeature<"ptx40", "PTXVersion", "40",
"Use PTX version 4.0">; "Use PTX version 4.0">;
def PTX41 : SubtargetFeature<"ptx41", "PTXVersion", "41", def PTX41 : SubtargetFeature<"ptx41", "PTXVersion", "41",
"Use PTX version 4.1">; "Use PTX version 4.1">;
def PTX42 : SubtargetFeature<"ptx42", "PTXVersion", "42", def PTX42 : SubtargetFeature<"ptx42", "PTXVersion", "42",
"Use PTX version 4.2">; "Use PTX version 4.2">;
def PTX43 : SubtargetFeature<"ptx43", "PTXVersion", "43",
"Use PTX version 4.3">;
def PTX50 : SubtargetFeature<"ptx50", "PTXVersion", "50",
"Use PTX version 5.0">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// NVPTX supported processors. // NVPTX supported processors.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class Proc<string Name, list<SubtargetFeature> Features> class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>; : Processor<Name, NoItineraries, Features>;
def : Proc<"sm_20", [SM20]>; def : Proc<"sm_20", [SM20]>;
def : Proc<"sm_21", [SM21]>; def : Proc<"sm_21", [SM21]>;
def : Proc<"sm_30", [SM30]>; def : Proc<"sm_30", [SM30]>;
def : Proc<"sm_32", [SM32, PTX40]>; def : Proc<"sm_32", [SM32, PTX40]>;
def : Proc<"sm_35", [SM35]>; def : Proc<"sm_35", [SM35]>;
def : Proc<"sm_37", [SM37, PTX41]>; def : Proc<"sm_37", [SM37, PTX41]>;
def : Proc<"sm_50", [SM50, PTX40]>; def : Proc<"sm_50", [SM50, PTX40]>;
def : Proc<"sm_52", [SM52, PTX41]>; def : Proc<"sm_52", [SM52, PTX41]>;
def : Proc<"sm_53", [SM53, PTX42]>; def : Proc<"sm_53", [SM53, PTX42]>;
def : Proc<"sm_60", [SM60, PTX50]>;
def : Proc<"sm_61", [SM61, PTX50]>;
def : Proc<"sm_62", [SM62, PTX50]>;
def NVPTXInstrInfo : InstrInfo { def NVPTXInstrInfo : InstrInfo {
} }
def NVPTX : Target { def NVPTX : Target {
let InstructionSet = NVPTXInstrInfo; let InstructionSet = NVPTXInstrInfo;
} }

llvm/trunk/test/CodeGen/NVPTX/sm-version-60.ll

; RUN: llc < %s -march=nvptx -mcpu=sm_60 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s
; CHECK: .version 5.0
; CHECK: .target sm_60

llvm/trunk/test/CodeGen/NVPTX/sm-version-61.ll

; RUN: llc < %s -march=nvptx -mcpu=sm_61 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_61 | FileCheck %s
; CHECK: .version 5.0
; CHECK: .target sm_61

llvm/trunk/test/CodeGen/NVPTX/sm-version-62.ll

; RUN: llc < %s -march=nvptx -mcpu=sm_62 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_62 | FileCheck %s
; CHECK: .version 5.0
; CHECK: .target sm_62