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Differential D22050

[SystemZ] Add support for missing instructions
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Authored by • zhanjunl on Jul 6 2016, 9:19 AM.

Details

Reviewers
uweigand
Commits
rG3b4c3f4d5164: [SystemZ] Add support for missing instructions
rL274869: [SystemZ] Add support for missing instructions
Summary

Add support to allow clang integrated assembler to recognize some missing instructions, for openssl.

Instructions are:
LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL.

Diff Detail

Event Timeline

• zhanjunl updated this revision to Diff 62885.Jul 6 2016, 9:19 AM
• zhanjunl retitled this revision from to [SystemZ] Add support for missing instructions.
• zhanjunl updated this object.
• zhanjunl added a reviewer: uweigand.
• zhanjunl added a subscriber: llvm-commits.
uweigand edited edge metadata.Jul 6 2016, 11:09 AM

See inline comments.

Also, when adding new instructions, you need to add disassembler tests as well (test/MC/Disassembler/SystemZ).

It would be nice to add not just single instructions you find missing somewhere, but full related groups of instructions where it makes sense. For example, when adding EX, it might be nice to also add EXRL. Similarly, when adding ICM(Y), it would be nice to also add ICMH, and possibly even STCM(Y/H) and CLCM(Y/H) as well. (To be clear: this is just a suggestion, not a requirement.)

lib/Target/SystemZ/SystemZInstrInfo.td
706

This should use a *Pair pattern like all other "y" instructions.

711

Likewise.

825

Please create a new TernaryRSPair for those (implemented similarly to TernaryRXF).

1381

These are just aliases for TMLL/TMLH, so it should be enough to define those via InstAlias.

1672

Don't need the { } for a single statement here.

• koriakin added a subscriber: • koriakin.Jul 6 2016, 11:49 AM
• koriakin added inline comments.
lib/Target/SystemZ/SystemZInstrInfo.td
1201

Don't give a pattern to this instruction - otherwise, ISel could use it to implement shl, which is incorrect.

• zhanjunl updated this revision to Diff 63226.Jul 8 2016, 8:33 AM
• zhanjunl edited edge metadata.

Updated the diff with fixes based on comments, to add *Pair classes, to use InstAlias, and to remove the pattern from SLA. Also added EXRL, ICMH, STMH, LMH, and added disassembler tests.

uweigand accepted this revision.Jul 8 2016, 8:46 AM
uweigand edited edge metadata.

See the inline comment. Otherwise, LGTM. Thanks!

lib/Target/SystemZ/SystemZInstrInfo.td
823

ICMH also should be in the Defs = [CC] clause.

This revision is now accepted and ready to land.Jul 8 2016, 8:46 AM
• zhanjunl updated this revision to Diff 63240.Jul 8 2016, 9:05 AM
• zhanjunl updated this object.
• zhanjunl edited edge metadata.

Whoops you're right, I've added ICMH to the Defs = [CC] clause.

• zhanjunl marked 7 inline comments as done.Jul 8 2016, 9:06 AM
uweigand added a comment.Jul 8 2016, 9:10 AM

LGTM, thanks!

Closed by commit rL274869: [SystemZ] Add support for missing instructions (authored by • zhanjunl). · Explain WhyJul 8 2016, 9:26 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
SystemZ/
12 lines
22 lines
test/
MC/
SystemZ/
14 lines
109 lines
26 lines
192 lines

Diff 62885

lib/Target/SystemZ/SystemZInstrFormats.td

Show First 20 Lines • Show All 1,050 Lines • ▼ Show 20 Linesclass BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
: InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2), : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
mnemonic##"\t$R1, $I2", []> { mnemonic##"\t$R1, $I2", []> {
let isBranch = 1; let isBranch = 1;
let isTerminator = 1; let isTerminator = 1;
let Constraints = "$R1 = $R1src"; let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src"; let DisableEncoding = "$R1src";
} }
class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
: InstRS<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr12only:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayLoad = 1;
}
class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2), : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> { mnemonic#"\t$R1, $R3, $BD2", []> {
let mayLoad = 1; let mayLoad = 1;
} }
class LoadMultipleVRSa<string mnemonic, bits<16> opcode> class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
: InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2), : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Linesclass StoreLengthVRSb<string mnemonic, bits<16> opcode,
: InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2), : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
mnemonic#"\t$V1, $R3, $BD2", mnemonic#"\t$V1, $R3, $BD2",
[(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
let M4 = 0; let M4 = 0;
let mayStore = 1; let mayStore = 1;
let AccessBytes = bytes; let AccessBytes = bytes;
} }
class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
: InstRS<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr12only:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let mayStore = 1;
}
class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2), : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> { mnemonic#"\t$R1, $R3, $BD2", []> {
let mayStore = 1; let mayStore = 1;
} }
class StoreMultipleVRSa<string mnemonic, bits<16> opcode> class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
: InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2), : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
▲ Show 20 Lines • Show All 1,393 Lines • Show Last 20 Lines

lib/Target/SystemZ/SystemZInstrInfo.td

Show First 20 Lines • Show All 696 Lines • ▼ Show 20 Lines
defm : StoreGR64Pair<ST, STY, truncstorei32>; defm : StoreGR64Pair<ST, STY, truncstorei32>;
def : StoreGR64PC<STRL, aligned_truncstorei32>; def : StoreGR64PC<STRL, aligned_truncstorei32>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Multi-register moves // Multi-register moves
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Multi-register loads. // Multi-register loads.
def LM : LoadMultipleRS<"lm", 0x98, GR32>;
def LMY : LoadMultipleRSY<"lmy", 0xEB98, GR32>;
uweigandUnsubmitted
Done
ReplyInline Actions

This should use a *Pair pattern like all other "y" instructions.

uweigand: This should use a *Pair pattern like all other "y" instructions.
def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
// Multi-register stores. // Multi-register stores.
def STM : StoreMultipleRS<"stm", 0x90, GR32>;
def STMY : StoreMultipleRSY<"stmy", 0xEB90, GR32>;
uweigandUnsubmitted
Done
ReplyInline Actions

Likewise.

uweigand: Likewise.
def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Byte swaps // Byte swaps
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Byte-swapping register moves. // Byte-swapping register moves.
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>;
defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>;
defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
let mayLoad = 1, Defs = [CC] in {
def ICM : InstRS<0xBF, (outs GR32:$R1), (ins imm32zx4:$R3, bdaddr12only:$BD2),
"icm\t$R1, $R3, $BD2", []>;
uweigandUnsubmitted
Done
ReplyInline Actions

ICMH also should be in the Defs = [CC] clause.

uweigand: ICMH also should be in the Defs = [CC] clause.
def ICMY : InstRSY<0xEB81, (outs GR32:$R1), (ins imm32zx4:$R3, bdaddr20only:$BD2),
"icmy\t$R1, $R3, $BD2", []>;
uweigandUnsubmitted
Done
ReplyInline Actions

Please create a new TernaryRSPair for those (implemented similarly to TernaryRXF).

uweigand: Please create a new TernaryRSPair for those (implemented similarly to TernaryRXF).
}
// Insertions of a 16-bit immediate, leaving other bits unaffected. // Insertions of a 16-bit immediate, leaving other bits unaffected.
// We don't have or_as_insert equivalents of these operations because // We don't have or_as_insert equivalents of these operations because
// OI is available instead. // OI is available instead.
// //
// IIxMux expands to II[LH]x, depending on the choice of register. // IIxMux expands to II[LH]x, depending on the choice of register.
def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
Requires<[FeatureHighWord]>; Requires<[FeatureHighWord]>;
def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
▲ Show 20 Lines • Show All 357 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Shifts // Shifts
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Shift left. // Shift left.
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, shl, GR32>;
koriakinUnsubmitted
Done
ReplyInline Actions

Don't give a pattern to this instruction - otherwise, ISel could use it to implement shl, which is incorrect.

koriakin: Don't give a pattern to this instruction - otherwise, ISel could use it to implement shl, which…
def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>;
} }
// Logical shift right. // Logical shift right.
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
} }
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lineslet Defs = [CC] in {
def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>;
def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>;
def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>;
def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>;
defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
let isAsmParserOnly=1 in {
def TML : CompareRI<"tml", 0xA71, z_tm_reg, GR32, imm32ll16>;
def TMH : CompareRI<"tmh", 0xA70, z_tm_reg, GR32, imm32lh16>;
uweigandUnsubmitted
Done
ReplyInline Actions

These are just aliases for TMLL/TMLH, so it should be enough to define those via InstAlias.

uweigand: These are just aliases for TMLL/TMLH, so it should be enough to define those via InstAlias.
} }
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Prefetch // Prefetch
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
▲ Show 20 Lines • Show All 268 Lines • ▼ Show 20 Lineslet hasSideEffects = 1, Defs = [CC], mayStore = 1 in
def STCKE : InstS<0xB278, (outs), (ins bdaddr12only:$BD2), def STCKE : InstS<0xB278, (outs), (ins bdaddr12only:$BD2),
"stcke\t$BD2", "stcke\t$BD2",
[]>; []>;
let hasSideEffects = 1, Defs = [CC], mayStore = 1 in let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
def STFLE : InstS<0xB2B0, (outs), (ins bdaddr12only:$BD2), def STFLE : InstS<0xB2B0, (outs), (ins bdaddr12only:$BD2),
"stfle\t$BD2", "stfle\t$BD2",
[]>; []>;
let hasSideEffects = 1 in {
def EX : InstRX<0x44, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
"ex\t$R1, $XBD2", []>;
}
uweigandUnsubmitted
Done
ReplyInline Actions

Don't need the { } for a single statement here.

uweigand: Don't need the { } for a single statement here.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Peepholes. // Peepholes.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Use AL* for GR64 additions of unsigned 32-bit values. // Use AL* for GR64 additions of unsigned 32-bit values.
defm : ZXB<add, GR64, ALGFR>; defm : ZXB<add, GR64, ALGFR>;
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

test/MC/SystemZ/insn-bad-z196.s

Show First 20 Lines • Show All 601 Lines • ▼ Show 20 Lines#CHECK: risblg %r0,%r0,256,0,0
risblg %r0,%r0,0,0,-1 risblg %r0,%r0,0,0,-1
risblg %r0,%r0,0,0,64 risblg %r0,%r0,0,0,64
risblg %r0,%r0,0,-1,0 risblg %r0,%r0,0,-1,0
risblg %r0,%r0,0,256,0 risblg %r0,%r0,0,256,0
risblg %r0,%r0,-1,0,0 risblg %r0,%r0,-1,0,0
risblg %r0,%r0,256,0,0 risblg %r0,%r0,256,0,0
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: slak %r0,%r0,-524289
#CHECK: error: invalid operand
#CHECK: slak %r0,%r0,524288
#CHECK: error: %r0 used in an address
#CHECK: slak %r0,%r0,0(%r0)
#CHECK: error: invalid use of indexed addressing
#CHECK: slak %r0,%r0,0(%r1,%r2)
slak %r0,%r0,-524289
slak %r0,%r0,524288
slak %r0,%r0,0(%r0)
slak %r0,%r0,0(%r1,%r2)
#CHECK: error: invalid operand
#CHECK: sllk %r0,%r0,-524289 #CHECK: sllk %r0,%r0,-524289
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: sllk %r0,%r0,524288 #CHECK: sllk %r0,%r0,524288
#CHECK: error: %r0 used in an address #CHECK: error: %r0 used in an address
#CHECK: sllk %r0,%r0,0(%r0) #CHECK: sllk %r0,%r0,0(%r0)
#CHECK: error: invalid use of indexed addressing #CHECK: error: invalid use of indexed addressing
#CHECK: sllk %r0,%r0,0(%r1,%r2) #CHECK: sllk %r0,%r0,0(%r1,%r2)
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines

test/MC/SystemZ/insn-bad.s

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#CHECK: dxbr %f0, %f2 #CHECK: dxbr %f0, %f2
#CHECK: error: invalid register pair #CHECK: error: invalid register pair
#CHECK: dxbr %f2, %f0 #CHECK: dxbr %f2, %f0
dxbr %f0, %f2 dxbr %f0, %f2
dxbr %f2, %f0 dxbr %f2, %f0
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: ex %r0, -1
#CHECK: error: invalid operand
#CHECK: ex %r0, 4096
ex %r0, -1
ex %r0, 4096
#CHECK: error: invalid operand
#CHECK: fidbr %f0, -1, %f0 #CHECK: fidbr %f0, -1, %f0
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: fidbr %f0, 16, %f0 #CHECK: fidbr %f0, 16, %f0
fidbr %f0, -1, %f0 fidbr %f0, -1, %f0
fidbr %f0, 16, %f0 fidbr %f0, 16, %f0
#CHECK: error: {{(instruction requires: fp-extension)?}} #CHECK: error: {{(instruction requires: fp-extension)?}}
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
#CHECK: ic %r0, -1 #CHECK: ic %r0, -1
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: ic %r0, 4096 #CHECK: ic %r0, 4096
ic %r0, -1 ic %r0, -1
ic %r0, 4096 ic %r0, 4096
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: icm %r0, 0, -1
#CHECK: error: invalid operand
#CHECK: icm %r0, 0, 4096
#CHECK: error: invalid operand
#CHECK: icm %r0, -1, 0
#CHECK: error: invalid operand
#CHECK: icm %r0, 16, 0
icm %r0, 0, -1
icm %r0, 0, 4096
icm %r0, -1, 0
icm %r0, 16, 0
#CHECK: error: invalid operand
#CHECK: icmy %r0, 0, -524289
#CHECK: error: invalid operand
#CHECK: icmy %r0, 0, 524288
#CHECK: error: invalid operand
#CHECK: icmy %r0, -1, 0
#CHECK: error: invalid operand
#CHECK: icmy %r0, 16, 0
icmy %r0, 0, -524289
icmy %r0, 0, 524288
icmy %r0, -1, 0
icmy %r0, 16, 0
#CHECK: error: invalid operand
#CHECK: icy %r0, -524289 #CHECK: icy %r0, -524289
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: icy %r0, 524288 #CHECK: icy %r0, 524288
icy %r0, -524289 icy %r0, -524289
icy %r0, 524288 icy %r0, 524288
#CHECK: error: invalid operand #CHECK: error: invalid operand
▲ Show 20 Lines • Show All 494 Lines • ▼ Show 20 Lines
#CHECK: llill %r0, -1 #CHECK: llill %r0, -1
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: llill %r0, 0x10000 #CHECK: llill %r0, 0x10000
llill %r0, -1 llill %r0, -1
llill %r0, 0x10000 llill %r0, 0x10000
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: lm %r0, %r0, 4096
#CHECK: error: invalid use of indexed addressing
#CHECK: lm %r0, %r0, 0(%r1,%r2)
lm %r0, %r0, 4096
lm %r0, %r0, 0(%r1,%r2)
#CHECK: error: invalid operand
#CHECK: lmg %r0, %r0, -524289 #CHECK: lmg %r0, %r0, -524289
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: lmg %r0, %r0, 524288 #CHECK: lmg %r0, %r0, 524288
#CHECK: error: invalid use of indexed addressing #CHECK: error: invalid use of indexed addressing
#CHECK: lmg %r0, %r0, 0(%r1,%r2) #CHECK: lmg %r0, %r0, 0(%r1,%r2)
lmg %r0, %r0, -524289 lmg %r0, %r0, -524289
lmg %r0, %r0, 524288 lmg %r0, %r0, 524288
lmg %r0, %r0, 0(%r1,%r2) lmg %r0, %r0, 0(%r1,%r2)
#CHECK: error: invalid operand
#CHECK: lmy %r0, %r0, -524289
#CHECK: error: invalid operand
#CHECK: lmy %r0, %r0, 524288
#CHECK: error: invalid use of indexed addressing
#CHECK: lmy %r0, %r0, 0(%r1,%r2)
lmy %r0, %r0, -524289
lmy %r0, %r0, 524288
lmy %r0, %r0, 0(%r1,%r2)
#CHECK: error: invalid register pair #CHECK: error: invalid register pair
#CHECK: lnxbr %f0, %f2 #CHECK: lnxbr %f0, %f2
#CHECK: error: invalid register pair #CHECK: error: invalid register pair
#CHECK: lnxbr %f2, %f0 #CHECK: lnxbr %f2, %f0
lnxbr %f0, %f2 lnxbr %f0, %f2
lnxbr %f2, %f0 lnxbr %f2, %f0
▲ Show 20 Lines • Show All 994 Lines • ▼ Show 20 Lines#CHECK: slgfi %r0, (1 << 32)
slgfi %r0, (1 << 32) slgfi %r0, (1 << 32)
#CHECK: error: {{(instruction requires: distinct-ops)?}} #CHECK: error: {{(instruction requires: distinct-ops)?}}
#CHECK: slgrk %r2,%r3,%r4 #CHECK: slgrk %r2,%r3,%r4
slgrk %r2,%r3,%r4 slgrk %r2,%r3,%r4
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: sla %r0,-1
#CHECK: error: invalid operand
#CHECK: sla %r0,4096
#CHECK: error: %r0 used in an address
#CHECK: sla %r0,0(%r0)
#CHECK: error: invalid use of indexed addressing
#CHECK: sla %r0,0(%r1,%r2)
sla %r0,-1
sla %r0,4096
sla %r0,0(%r0)
sla %r0,0(%r1,%r2)
#CHECK: error: {{(instruction requires: distinct-ops)?}}
#CHECK: slak %r2,%r3,4(%r5)
slak %r2,%r3,4(%r5)
#CHECK: error: invalid operand
#CHECK: sll %r0,-1 #CHECK: sll %r0,-1
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: sll %r0,4096 #CHECK: sll %r0,4096
#CHECK: error: %r0 used in an address #CHECK: error: %r0 used in an address
#CHECK: sll %r0,0(%r0) #CHECK: sll %r0,0(%r0)
#CHECK: error: invalid use of indexed addressing #CHECK: error: invalid use of indexed addressing
#CHECK: sll %r0,0(%r1,%r2) #CHECK: sll %r0,0(%r1,%r2)
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Lines#CHECK: sthy %r0, 524288
sthy %r0, 524288 sthy %r0, 524288
#CHECK: error: {{(instruction requires: high-word)?}} #CHECK: error: {{(instruction requires: high-word)?}}
#CHECK: stfh %r0, 0 #CHECK: stfh %r0, 0
stfh %r0, 0 stfh %r0, 0
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: stm %r0, %r0, 4096
#CHECK: error: invalid use of indexed addressing
#CHECK: stm %r0, %r0, 0(%r1,%r2)
stm %r0, %r0, 4096
stm %r0, %r0, 0(%r1,%r2)
#CHECK: error: invalid operand
#CHECK: stmg %r0, %r0, -524289 #CHECK: stmg %r0, %r0, -524289
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: stmg %r0, %r0, 524288 #CHECK: stmg %r0, %r0, 524288
#CHECK: error: invalid use of indexed addressing #CHECK: error: invalid use of indexed addressing
#CHECK: stmg %r0, %r0, 0(%r1,%r2) #CHECK: stmg %r0, %r0, 0(%r1,%r2)
stmg %r0, %r0, -524289 stmg %r0, %r0, -524289
stmg %r0, %r0, 524288 stmg %r0, %r0, 524288
stmg %r0, %r0, 0(%r1,%r2) stmg %r0, %r0, 0(%r1,%r2)
#CHECK: error: invalid operand
#CHECK: stmy %r0, %r0, -524289
#CHECK: error: invalid operand
#CHECK: stmy %r0, %r0, 524288
#CHECK: error: invalid use of indexed addressing
#CHECK: stmy %r0, %r0, 0(%r1,%r2)
stmy %r0, %r0, -524289
stmy %r0, %r0, 524288
stmy %r0, %r0, 0(%r1,%r2)
#CHECK: error: offset out of range #CHECK: error: offset out of range
#CHECK: strl %r0, -0x1000000002 #CHECK: strl %r0, -0x1000000002
#CHECK: error: offset out of range #CHECK: error: offset out of range
#CHECK: strl %r0, -1 #CHECK: strl %r0, -1
#CHECK: error: offset out of range #CHECK: error: offset out of range
#CHECK: strl %r0, 1 #CHECK: strl %r0, 1
#CHECK: error: offset out of range #CHECK: error: offset out of range
#CHECK: strl %r0, 0x100000000 #CHECK: strl %r0, 0x100000000
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
#CHECK: tmhl %r0, -1 #CHECK: tmhl %r0, -1
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: tmhl %r0, 0x10000 #CHECK: tmhl %r0, 0x10000
tmhl %r0, -1 tmhl %r0, -1
tmhl %r0, 0x10000 tmhl %r0, 0x10000
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: tmh %r0, -1
#CHECK: error: invalid operand
#CHECK: tmh %r0, 0x10000
tmh %r0, -1
tmh %r0, 0x10000
#CHECK: error: invalid operand
#CHECK: tmlh %r0, -1 #CHECK: tmlh %r0, -1
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: tmlh %r0, 0x10000 #CHECK: tmlh %r0, 0x10000
tmlh %r0, -1 tmlh %r0, -1
tmlh %r0, 0x10000 tmlh %r0, 0x10000
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: tml %r0, -1
#CHECK: error: invalid operand
#CHECK: tml %r0, 0x10000
tml %r0, -1
tml %r0, 0x10000
#CHECK: error: invalid operand
#CHECK: tmll %r0, -1 #CHECK: tmll %r0, -1
#CHECK: error: invalid operand #CHECK: error: invalid operand
#CHECK: tmll %r0, 0x10000 #CHECK: tmll %r0, 0x10000
tmll %r0, -1 tmll %r0, -1
tmll %r0, 0x10000 tmll %r0, 0x10000
#CHECK: error: invalid operand #CHECK: error: invalid operand
▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines

test/MC/SystemZ/insn-good-z196.s

Show First 20 Lines • Show All 1,117 Lines • ▼ Show 20 Lines
#CHECK: sgrk %r7, %r8, %r9 # encoding: [0xb9,0xe9,0x90,0x78] #CHECK: sgrk %r7, %r8, %r9 # encoding: [0xb9,0xe9,0x90,0x78]
sgrk %r0,%r0,%r0 sgrk %r0,%r0,%r0
sgrk %r0,%r0,%r15 sgrk %r0,%r0,%r15
sgrk %r0,%r15,%r0 sgrk %r0,%r15,%r0
sgrk %r15,%r0,%r0 sgrk %r15,%r0,%r0
sgrk %r7,%r8,%r9 sgrk %r7,%r8,%r9
#CHECK: slak %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0xdd]
#CHECK: slak %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xdd]
#CHECK: slak %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xdd]
#CHECK: slak %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0xdd]
#CHECK: slak %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0xdd]
#CHECK: slak %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0xdd]
#CHECK: slak %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0xdd]
#CHECK: slak %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xdd]
#CHECK: slak %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0xdd]
#CHECK: slak %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xdd]
#CHECK: slak %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0xdd]
#CHECK: slak %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0xdd]
slak %r0,%r0,0
slak %r15,%r1,0
slak %r1,%r15,0
slak %r15,%r15,0
slak %r0,%r0,-524288
slak %r0,%r0,-1
slak %r0,%r0,1
slak %r0,%r0,524287
slak %r0,%r0,0(%r1)
slak %r0,%r0,0(%r15)
slak %r0,%r0,524287(%r1)
slak %r0,%r0,524287(%r15)
#CHECK: slgrk %r0, %r0, %r0 # encoding: [0xb9,0xeb,0x00,0x00] #CHECK: slgrk %r0, %r0, %r0 # encoding: [0xb9,0xeb,0x00,0x00]
#CHECK: slgrk %r0, %r0, %r15 # encoding: [0xb9,0xeb,0xf0,0x00] #CHECK: slgrk %r0, %r0, %r15 # encoding: [0xb9,0xeb,0xf0,0x00]
#CHECK: slgrk %r0, %r15, %r0 # encoding: [0xb9,0xeb,0x00,0x0f] #CHECK: slgrk %r0, %r15, %r0 # encoding: [0xb9,0xeb,0x00,0x0f]
#CHECK: slgrk %r15, %r0, %r0 # encoding: [0xb9,0xeb,0x00,0xf0] #CHECK: slgrk %r15, %r0, %r0 # encoding: [0xb9,0xeb,0x00,0xf0]
#CHECK: slgrk %r7, %r8, %r9 # encoding: [0xb9,0xeb,0x90,0x78] #CHECK: slgrk %r7, %r8, %r9 # encoding: [0xb9,0xeb,0x90,0x78]
slgrk %r0,%r0,%r0 slgrk %r0,%r0,%r0
slgrk %r0,%r0,%r15 slgrk %r0,%r0,%r15
▲ Show 20 Lines • Show All 315 Lines • Show Last 20 Lines

test/MC/SystemZ/insn-good.s

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,320 Lines • ▼ Show 20 Lines
#CHECK: ear %r15, %a15 # encoding: [0xb2,0x4f,0x00,0xff] #CHECK: ear %r15, %a15 # encoding: [0xb2,0x4f,0x00,0xff]
ear %r0, %a0 ear %r0, %a0
ear %r0, %a15 ear %r0, %a15
ear %r15, %a0 ear %r15, %a0
ear %r7, %a8 ear %r7, %a8
ear %r15, %a15 ear %r15, %a15
#CHECK: ex %r0, 0 # encoding: [0x44,0x00,0x00,0x00]
#CHECK: ex %r0, 4095 # encoding: [0x44,0x00,0x0f,0xff]
#CHECK: ex %r0, 0(%r1) # encoding: [0x44,0x00,0x10,0x00]
#CHECK: ex %r0, 0(%r15) # encoding: [0x44,0x00,0xf0,0x00]
#CHECK: ex %r0, 4095(%r1,%r15) # encoding: [0x44,0x01,0xff,0xff]
#CHECK: ex %r0, 4095(%r15,%r1) # encoding: [0x44,0x0f,0x1f,0xff]
#CHECK: ex %r15, 0 # encoding: [0x44,0xf0,0x00,0x00]
ex %r0, 0
ex %r0, 4095
ex %r0, 0(%r1)
ex %r0, 0(%r15)
ex %r0, 4095(%r1,%r15)
ex %r0, 4095(%r15,%r1)
ex %r15, 0
#CHECK: fidbr %f0, 0, %f0 # encoding: [0xb3,0x5f,0x00,0x00] #CHECK: fidbr %f0, 0, %f0 # encoding: [0xb3,0x5f,0x00,0x00]
#CHECK: fidbr %f0, 0, %f15 # encoding: [0xb3,0x5f,0x00,0x0f] #CHECK: fidbr %f0, 0, %f15 # encoding: [0xb3,0x5f,0x00,0x0f]
#CHECK: fidbr %f0, 15, %f0 # encoding: [0xb3,0x5f,0xf0,0x00] #CHECK: fidbr %f0, 15, %f0 # encoding: [0xb3,0x5f,0xf0,0x00]
#CHECK: fidbr %f4, 5, %f6 # encoding: [0xb3,0x5f,0x50,0x46] #CHECK: fidbr %f4, 5, %f6 # encoding: [0xb3,0x5f,0x50,0x46]
#CHECK: fidbr %f15, 0, %f0 # encoding: [0xb3,0x5f,0x00,0xf0] #CHECK: fidbr %f15, 0, %f0 # encoding: [0xb3,0x5f,0x00,0xf0]
fidbr %f0, 0, %f0 fidbr %f0, 0, %f0
fidbr %f0, 0, %f15 fidbr %f0, 0, %f15
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines#CHECK: ic %r15, 0 # encoding: [0x43,0xf0,0x00,0x00]
ic %r0, 0 ic %r0, 0
ic %r0, 4095 ic %r0, 4095
ic %r0, 0(%r1) ic %r0, 0(%r1)
ic %r0, 0(%r15) ic %r0, 0(%r15)
ic %r0, 4095(%r1,%r15) ic %r0, 4095(%r1,%r15)
ic %r0, 4095(%r15,%r1) ic %r0, 4095(%r15,%r1)
ic %r15, 0 ic %r15, 0
#CHECK: icm %r0, 0, 0 # encoding: [0xbf,0x00,0x00,0x00]
#CHECK: icm %r0, 15, 4095 # encoding: [0xbf,0x0f,0x0f,0xff]
#CHECK: icm %r0, 0, 0(%r1) # encoding: [0xbf,0x00,0x10,0x00]
#CHECK: icm %r0, 0, 0(%r15) # encoding: [0xbf,0x00,0xf0,0x00]
#CHECK: icm %r15, 15, 4095(%r1) # encoding: [0xbf,0xff,0x1f,0xff]
#CHECK: icm %r0, 0, 4095(%r15) # encoding: [0xbf,0x00,0xff,0xff]
#CHECK: icm %r15, 0, 0 # encoding: [0xbf,0xf0,0x00,0x00]
icm %r0, 0, 0
icm %r0, 15, 4095
icm %r0, 0, 0(%r1)
icm %r0, 0, 0(%r15)
icm %r15, 15, 4095(%r1)
icm %r0, 0, 4095(%r15)
icm %r15, 0, 0
#CHECK: icmy %r0, 0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x81]
#CHECK: icmy %r0, 0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x81]
#CHECK: icmy %r0, 15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x81]
#CHECK: icmy %r0, 15, 1 # encoding: [0xeb,0x0f,0x00,0x01,0x00,0x81]
#CHECK: icmy %r0, 8, 524287 # encoding: [0xeb,0x08,0x0f,0xff,0x7f,0x81]
#CHECK: icmy %r0, 8, 0(%r1) # encoding: [0xeb,0x08,0x10,0x00,0x00,0x81]
#CHECK: icmy %r0, 4, 0(%r15) # encoding: [0xeb,0x04,0xf0,0x00,0x00,0x81]
#CHECK: icmy %r0, 4, 524287(%r15) # encoding: [0xeb,0x04,0xff,0xff,0x7f,0x81]
#CHECK: icmy %r0, 0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x81]
#CHECK: icmy %r15, 0, 0 # encoding: [0xeb,0xf0,0x00,0x00,0x00,0x81]
icmy %r0, 0, -524288
icmy %r0, 0, -1
icmy %r0, 15, 0
icmy %r0, 15, 1
icmy %r0, 8, 524287
icmy %r0, 8, 0(%r1)
icmy %r0, 4, 0(%r15)
icmy %r0, 4, 524287(%r15)
icmy %r0, 0, 524287(%r1)
icmy %r15, 0, 0
#CHECK: icy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x73] #CHECK: icy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x73]
#CHECK: icy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x73] #CHECK: icy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x73]
#CHECK: icy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x73] #CHECK: icy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x73]
#CHECK: icy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x73] #CHECK: icy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x73]
#CHECK: icy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x73] #CHECK: icy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x73]
#CHECK: icy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x73] #CHECK: icy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x73]
#CHECK: icy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x73] #CHECK: icy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x73]
#CHECK: icy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x73] #CHECK: icy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x73]
▲ Show 20 Lines • Show All 1,112 Lines • ▼ Show 20 Lines
#CHECK: llill %r0, 65535 # encoding: [0xa5,0x0f,0xff,0xff] #CHECK: llill %r0, 65535 # encoding: [0xa5,0x0f,0xff,0xff]
#CHECK: llill %r15, 0 # encoding: [0xa5,0xff,0x00,0x00] #CHECK: llill %r15, 0 # encoding: [0xa5,0xff,0x00,0x00]
llill %r0, 0 llill %r0, 0
llill %r0, 0x8000 llill %r0, 0x8000
llill %r0, 0xffff llill %r0, 0xffff
llill %r15, 0 llill %r15, 0
#CHECK: lm %r0, %r0, 0 # encoding: [0x98,0x00,0x00,0x00]
#CHECK: lm %r0, %r15, 0 # encoding: [0x98,0x0f,0x00,0x00]
#CHECK: lm %r14, %r15, 0 # encoding: [0x98,0xef,0x00,0x00]
#CHECK: lm %r15, %r15, 0 # encoding: [0x98,0xff,0x00,0x00]
#CHECK: lm %r0, %r0, 4095 # encoding: [0x98,0x00,0x0f,0xff]
#CHECK: lm %r0, %r0, 1 # encoding: [0x98,0x00,0x00,0x01]
#CHECK: lm %r0, %r0, 0(%r1) # encoding: [0x98,0x00,0x10,0x00]
#CHECK: lm %r0, %r0, 0(%r15) # encoding: [0x98,0x00,0xf0,0x00]
#CHECK: lm %r0, %r0, 4095(%r1) # encoding: [0x98,0x00,0x1f,0xff]
#CHECK: lm %r0, %r0, 4095(%r15) # encoding: [0x98,0x00,0xff,0xff]
lm %r0,%r0,0
lm %r0,%r15,0
lm %r14,%r15,0
lm %r15,%r15,0
lm %r0,%r0,4095
lm %r0,%r0,1
lm %r0,%r0,0(%r1)
lm %r0,%r0,0(%r15)
lm %r0,%r0,4095(%r1)
lm %r0,%r0,4095(%r15)
#CHECK: lmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x04] #CHECK: lmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x04]
#CHECK: lmg %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x04] #CHECK: lmg %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x04]
#CHECK: lmg %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x04] #CHECK: lmg %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x04]
#CHECK: lmg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x04] #CHECK: lmg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x04]
#CHECK: lmg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x04] #CHECK: lmg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x04]
#CHECK: lmg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x04] #CHECK: lmg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x04]
#CHECK: lmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x04] #CHECK: lmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x04]
#CHECK: lmg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x04] #CHECK: lmg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x04]
Show All 12 Lines#CHECK: lmg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x04]
lmg %r0,%r0,0 lmg %r0,%r0,0
lmg %r0,%r0,1 lmg %r0,%r0,1
lmg %r0,%r0,524287 lmg %r0,%r0,524287
lmg %r0,%r0,0(%r1) lmg %r0,%r0,0(%r1)
lmg %r0,%r0,0(%r15) lmg %r0,%r0,0(%r15)
lmg %r0,%r0,524287(%r1) lmg %r0,%r0,524287(%r1)
lmg %r0,%r0,524287(%r15) lmg %r0,%r0,524287(%r15)
#CHECK: lmy %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x98]
#CHECK: lmy %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x98]
#CHECK: lmy %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x98]
#CHECK: lmy %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x98]
#CHECK: lmy %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x98]
#CHECK: lmy %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x98]
#CHECK: lmy %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x98]
#CHECK: lmy %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x98]
#CHECK: lmy %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x98]
#CHECK: lmy %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x98]
#CHECK: lmy %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x98]
#CHECK: lmy %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x98]
#CHECK: lmy %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x98]
lmy %r0,%r0,0
lmy %r0,%r15,0
lmy %r14,%r15,0
lmy %r15,%r15,0
lmy %r0,%r0,-524288
lmy %r0,%r0,-1
lmy %r0,%r0,0
lmy %r0,%r0,1
lmy %r0,%r0,524287
lmy %r0,%r0,0(%r1)
lmy %r0,%r0,0(%r15)
lmy %r0,%r0,524287(%r1)
lmy %r0,%r0,524287(%r15)
#CHECK: lndbr %f0, %f9 # encoding: [0xb3,0x11,0x00,0x09] #CHECK: lndbr %f0, %f9 # encoding: [0xb3,0x11,0x00,0x09]
#CHECK: lndbr %f0, %f15 # encoding: [0xb3,0x11,0x00,0x0f] #CHECK: lndbr %f0, %f15 # encoding: [0xb3,0x11,0x00,0x0f]
#CHECK: lndbr %f15, %f0 # encoding: [0xb3,0x11,0x00,0xf0] #CHECK: lndbr %f15, %f0 # encoding: [0xb3,0x11,0x00,0xf0]
#CHECK: lndbr %f15, %f9 # encoding: [0xb3,0x11,0x00,0xf9] #CHECK: lndbr %f15, %f9 # encoding: [0xb3,0x11,0x00,0xf9]
lndbr %f0,%f9 lndbr %f0,%f9
lndbr %f0,%f15 lndbr %f0,%f15
lndbr %f15,%f0 lndbr %f15,%f0
▲ Show 20 Lines • Show All 1,968 Lines • ▼ Show 20 Lines
#CHECK: slgr %r15, %r0 # encoding: [0xb9,0x0b,0x00,0xf0] #CHECK: slgr %r15, %r0 # encoding: [0xb9,0x0b,0x00,0xf0]
#CHECK: slgr %r7, %r8 # encoding: [0xb9,0x0b,0x00,0x78] #CHECK: slgr %r7, %r8 # encoding: [0xb9,0x0b,0x00,0x78]
slgr %r0,%r0 slgr %r0,%r0
slgr %r0,%r15 slgr %r0,%r15
slgr %r15,%r0 slgr %r15,%r0
slgr %r7,%r8 slgr %r7,%r8
#CHECK: sla %r0, 0 # encoding: [0x8b,0x00,0x00,0x00]
#CHECK: sla %r7, 0 # encoding: [0x8b,0x70,0x00,0x00]
#CHECK: sla %r15, 0 # encoding: [0x8b,0xf0,0x00,0x00]
#CHECK: sla %r0, 4095 # encoding: [0x8b,0x00,0x0f,0xff]
#CHECK: sla %r0, 0(%r1) # encoding: [0x8b,0x00,0x10,0x00]
#CHECK: sla %r0, 0(%r15) # encoding: [0x8b,0x00,0xf0,0x00]
#CHECK: sla %r0, 4095(%r1) # encoding: [0x8b,0x00,0x1f,0xff]
#CHECK: sla %r0, 4095(%r15) # encoding: [0x8b,0x00,0xff,0xff]
sla %r0,0
sla %r7,0
sla %r15,0
sla %r0,4095
sla %r0,0(%r1)
sla %r0,0(%r15)
sla %r0,4095(%r1)
sla %r0,4095(%r15)
#CHECK: sll %r0, 0 # encoding: [0x89,0x00,0x00,0x00] #CHECK: sll %r0, 0 # encoding: [0x89,0x00,0x00,0x00]
#CHECK: sll %r7, 0 # encoding: [0x89,0x70,0x00,0x00] #CHECK: sll %r7, 0 # encoding: [0x89,0x70,0x00,0x00]
#CHECK: sll %r15, 0 # encoding: [0x89,0xf0,0x00,0x00] #CHECK: sll %r15, 0 # encoding: [0x89,0xf0,0x00,0x00]
#CHECK: sll %r0, 4095 # encoding: [0x89,0x00,0x0f,0xff] #CHECK: sll %r0, 4095 # encoding: [0x89,0x00,0x0f,0xff]
#CHECK: sll %r0, 0(%r1) # encoding: [0x89,0x00,0x10,0x00] #CHECK: sll %r0, 0(%r1) # encoding: [0x89,0x00,0x10,0x00]
#CHECK: sll %r0, 0(%r15) # encoding: [0x89,0x00,0xf0,0x00] #CHECK: sll %r0, 0(%r15) # encoding: [0x89,0x00,0xf0,0x00]
#CHECK: sll %r0, 4095(%r1) # encoding: [0x89,0x00,0x1f,0xff] #CHECK: sll %r0, 4095(%r1) # encoding: [0x89,0x00,0x1f,0xff]
#CHECK: sll %r0, 4095(%r15) # encoding: [0x89,0x00,0xff,0xff] #CHECK: sll %r0, 4095(%r15) # encoding: [0x89,0x00,0xff,0xff]
▲ Show 20 Lines • Show All 550 Lines • ▼ Show 20 Lines#CHECK: sthy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x70]
sthy %r0, 1 sthy %r0, 1
sthy %r0, 524287 sthy %r0, 524287
sthy %r0, 0(%r1) sthy %r0, 0(%r1)
sthy %r0, 0(%r15) sthy %r0, 0(%r15)
sthy %r0, 524287(%r1,%r15) sthy %r0, 524287(%r1,%r15)
sthy %r0, 524287(%r15,%r1) sthy %r0, 524287(%r15,%r1)
sthy %r15, 0 sthy %r15, 0
#CHECK: stm %r0, %r0, 0 # encoding: [0x90,0x00,0x00,0x00]
#CHECK: stm %r0, %r15, 0 # encoding: [0x90,0x0f,0x00,0x00]
#CHECK: stm %r14, %r15, 0 # encoding: [0x90,0xef,0x00,0x00]
#CHECK: stm %r15, %r15, 0 # encoding: [0x90,0xff,0x00,0x00]
#CHECK: stm %r0, %r0, 4095 # encoding: [0x90,0x00,0x0f,0xff]
#CHECK: stm %r0, %r0, 1 # encoding: [0x90,0x00,0x00,0x01]
#CHECK: stm %r0, %r0, 0(%r1) # encoding: [0x90,0x00,0x10,0x00]
#CHECK: stm %r0, %r0, 0(%r15) # encoding: [0x90,0x00,0xf0,0x00]
#CHECK: stm %r0, %r0, 4095(%r1) # encoding: [0x90,0x00,0x1f,0xff]
#CHECK: stm %r0, %r0, 4095(%r15) # encoding: [0x90,0x00,0xff,0xff]
stm %r0,%r0,0
stm %r0,%r15,0
stm %r14,%r15,0
stm %r15,%r15,0
stm %r0,%r0,4095
stm %r0,%r0,1
stm %r0,%r0,0(%r1)
stm %r0,%r0,0(%r15)
stm %r0,%r0,4095(%r1)
stm %r0,%r0,4095(%r15)
#CHECK: stmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x24] #CHECK: stmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x24]
#CHECK: stmg %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x24] #CHECK: stmg %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x24]
#CHECK: stmg %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x24] #CHECK: stmg %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x24]
#CHECK: stmg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x24] #CHECK: stmg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x24]
#CHECK: stmg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x24] #CHECK: stmg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x24]
#CHECK: stmg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x24] #CHECK: stmg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x24]
#CHECK: stmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x24] #CHECK: stmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x24]
#CHECK: stmg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x24] #CHECK: stmg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x24]
Show All 12 Lines#CHECK: stmg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x24]
stmg %r0,%r0,0 stmg %r0,%r0,0
stmg %r0,%r0,1 stmg %r0,%r0,1
stmg %r0,%r0,524287 stmg %r0,%r0,524287
stmg %r0,%r0,0(%r1) stmg %r0,%r0,0(%r1)
stmg %r0,%r0,0(%r15) stmg %r0,%r0,0(%r15)
stmg %r0,%r0,524287(%r1) stmg %r0,%r0,524287(%r1)
stmg %r0,%r0,524287(%r15) stmg %r0,%r0,524287(%r15)
#CHECK: stmy %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x90]
#CHECK: stmy %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x90]
#CHECK: stmy %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x90]
#CHECK: stmy %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x90]
#CHECK: stmy %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x90]
#CHECK: stmy %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x90]
#CHECK: stmy %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x90]
#CHECK: stmy %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x90]
#CHECK: stmy %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x90]
#CHECK: stmy %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x90]
#CHECK: stmy %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x90]
#CHECK: stmy %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x90]
#CHECK: stmy %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x90]
stmy %r0,%r0,0
stmy %r0,%r15,0
stmy %r14,%r15,0
stmy %r15,%r15,0
stmy %r0,%r0,-524288
stmy %r0,%r0,-1
stmy %r0,%r0,0
stmy %r0,%r0,1
stmy %r0,%r0,524287
stmy %r0,%r0,0(%r1)
stmy %r0,%r0,0(%r15)
stmy %r0,%r0,524287(%r1)
stmy %r0,%r0,524287(%r15)
#CHECK: strl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0f,A,A,A,A] #CHECK: strl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0f,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL #CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
strl %r0, -0x100000000 strl %r0, -0x100000000
#CHECK: strl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x0f,A,A,A,A] #CHECK: strl %r0, .[[LAB:L.*]]-2 # encoding: [0xc4,0x0f,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL #CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL
strl %r0, -2 strl %r0, -2
#CHECK: strl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x0f,A,A,A,A] #CHECK: strl %r0, .[[LAB:L.*]] # encoding: [0xc4,0x0f,A,A,A,A]
#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL #CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL
▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
#CHECK: tmhl %r0, 65535 # encoding: [0xa7,0x03,0xff,0xff] #CHECK: tmhl %r0, 65535 # encoding: [0xa7,0x03,0xff,0xff]
#CHECK: tmhl %r15, 0 # encoding: [0xa7,0xf3,0x00,0x00] #CHECK: tmhl %r15, 0 # encoding: [0xa7,0xf3,0x00,0x00]
tmhl %r0, 0 tmhl %r0, 0
tmhl %r0, 0x8000 tmhl %r0, 0x8000
tmhl %r0, 0xffff tmhl %r0, 0xffff
tmhl %r15, 0 tmhl %r15, 0
#CHECK: tmh %r0, 0 # encoding: [0xa7,0x00,0x00,0x00]
#CHECK: tmh %r0, 32768 # encoding: [0xa7,0x00,0x80,0x00]
#CHECK: tmh %r0, 65535 # encoding: [0xa7,0x00,0xff,0xff]
#CHECK: tmh %r15, 0 # encoding: [0xa7,0xf0,0x00,0x00]
tmh %r0, 0
tmh %r0, 0x8000
tmh %r0, 0xffff
tmh %r15, 0
#CHECK: tmlh %r0, 0 # encoding: [0xa7,0x00,0x00,0x00] #CHECK: tmlh %r0, 0 # encoding: [0xa7,0x00,0x00,0x00]
#CHECK: tmlh %r0, 32768 # encoding: [0xa7,0x00,0x80,0x00] #CHECK: tmlh %r0, 32768 # encoding: [0xa7,0x00,0x80,0x00]
#CHECK: tmlh %r0, 65535 # encoding: [0xa7,0x00,0xff,0xff] #CHECK: tmlh %r0, 65535 # encoding: [0xa7,0x00,0xff,0xff]
#CHECK: tmlh %r15, 0 # encoding: [0xa7,0xf0,0x00,0x00] #CHECK: tmlh %r15, 0 # encoding: [0xa7,0xf0,0x00,0x00]
tmlh %r0, 0 tmlh %r0, 0
tmlh %r0, 0x8000 tmlh %r0, 0x8000
tmlh %r0, 0xffff tmlh %r0, 0xffff
tmlh %r15, 0 tmlh %r15, 0
#CHECK: tml %r0, 0 # encoding: [0xa7,0x01,0x00,0x00]
#CHECK: tml %r0, 32768 # encoding: [0xa7,0x01,0x80,0x00]
#CHECK: tml %r0, 65535 # encoding: [0xa7,0x01,0xff,0xff]
#CHECK: tml %r15, 0 # encoding: [0xa7,0xf1,0x00,0x00]
tml %r0, 0
tml %r0, 0x8000
tml %r0, 0xffff
tml %r15, 0
#CHECK: tmll %r0, 0 # encoding: [0xa7,0x01,0x00,0x00] #CHECK: tmll %r0, 0 # encoding: [0xa7,0x01,0x00,0x00]
#CHECK: tmll %r0, 32768 # encoding: [0xa7,0x01,0x80,0x00] #CHECK: tmll %r0, 32768 # encoding: [0xa7,0x01,0x80,0x00]
#CHECK: tmll %r0, 65535 # encoding: [0xa7,0x01,0xff,0xff] #CHECK: tmll %r0, 65535 # encoding: [0xa7,0x01,0xff,0xff]
#CHECK: tmll %r15, 0 # encoding: [0xa7,0xf1,0x00,0x00] #CHECK: tmll %r15, 0 # encoding: [0xa7,0xf1,0x00,0x00]
tmll %r0, 0 tmll %r0, 0
tmll %r0, 0x8000 tmll %r0, 0x8000
tmll %r0, 0xffff tmll %r0, 0xffff
▲ Show 20 Lines • Show All 183 Lines • Show Last 20 Lines