TailDuplicator: Remove live-in updating logic

[MatzeB]

Summary

This logic was introduced in r157663 and does not make any sense to me.
The motivating example in rdar://11538365 looks like this:

This is the tail:
BB#16: derived from LLVM BB %if.end68

Live Ins: %R0 %R4 %R5
Predecessors according to CFG: BB#15 BB#5
    tBLXi pred:14, pred:%noreg, <ga:@CFRelease>, %R0<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %SP<imp-def>
    t2B <BB#20>, pred:14, pred:%noreg
Successors according to CFG: BB#20

This is the predBB:
BB#5:

Live Ins: %R5
Predecessors according to CFG: BB#4
    %R4<def> = t2MOVi 0, pred:14, pred:%noreg, opt:%noreg
    t2B <BB#16>, pred:14, pred:%noreg
Successors according to CFG: BB#16

However this is invalid machine code to begin with, if %R0 is live-in to
BB#16 then it must be live-in to BB#5 as well if BB#5 does not define
it. We should not need logic to retroactively fix broken machine code
and in fact the example from r157663 passes cleanly today with the updating
code removed and I do not see any (newly) failing tests with the machine
verifier enabled.

[qcolombet]

Hi Matthias,

Yeah, that looks awful, thanks for the cleanup!

Cheers,
-Quentin

include/llvm/CodeGen/TailDuplicator.h

 
 /// Utility class to perform tail duplication.
 class TailDuplicator {
   const TargetInstrInfo *TII;
   const TargetRegisterInfo *TRI;
   const MachineBranchProbabilityInfo *MBPI;
   const MachineModuleInfo *MMI;
   MachineRegisterInfo *MRI;
-  std::unique_ptr<RegScavenger> RS;
   bool PreRegAlloc;
 
   // A list of virtual registers for which to update SSA form.
   SmallVector<unsigned, 16> SSAUpdateVRs;
 
   // For each virtual register in SSAUpdateVals keep a list of source virtual
   // registers.
   typedef std::vector<std::pair<MachineBasicBlock *, unsigned>> AvailableValsTy;

lib/CodeGen/TailDuplicator.cpp

void TailDuplicator::initMF(MachineFunction &MF, const MachineModuleInfo *MMIin,
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
   MMI = MMIin;
   MBPI = MBPIin;
 
   assert(MBPI != nullptr && "Machine Branch Probability Info required");
 
   PreRegAlloc = MRI->isSSA();
-  RS.reset();
-
-  if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
-    RS.reset(new RegScavenger());
 }
 
 static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
   for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ++I) {
     MachineBasicBlock *MBB = &*I;
     SmallSetVector<MachineBasicBlock *, 8> Preds(MBB->pred_begin(),
                                                  MBB->pred_end());
     MachineBasicBlock::iterator MI = MBB->begin();
for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(),
     DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
                  << "From Succ: " << *TailBB);
 
     TDBBs.push_back(PredBB);
 
     // Remove PredBB's unconditional branch.
     TII->RemoveBranch(*PredBB);
 
-    if (RS && !TailBB->livein_empty()) {
-      // Update PredBB livein.
-      RS->enterBasicBlock(*PredBB);
-      if (!PredBB->empty())
-        RS->forward(std::prev(PredBB->end()));
-      for (const auto &LI : TailBB->liveins()) {
-        if (!RS->isRegUsed(LI.PhysReg, false))
-          // If a register is previously livein to the tail but it's not live
-          // at the end of predecessor BB, then it should be added to its
-          // livein list.
-          PredBB->addLiveIn(LI);
-      }
-    }
-
     // Clone the contents of TailBB into PredBB.
     DenseMap<unsigned, RegSubRegPair> LocalVRMap;
     SmallVector<std::pair<unsigned, RegSubRegPair>, 4> CopyInfos;
     // Use instr_iterator here to properly handle bundles, e.g.
     // ARM Thumb2 IT block.
     MachineBasicBlock::instr_iterator I = TailBB->instr_begin();
     while (I != TailBB->instr_end()) {
       MachineInstr *MI = &*I;