This is an archive of the discontinued LLVM Phabricator instance.

Differential D22006

AMDGPU: Use implicit_def for selecting anyext
ClosedPublic

Authored by arsenm on Jul 5 2016, 12:02 PM.

Details

Reviewers
• tstellarAMD

Diff Detail

Event Timeline

arsenm updated this revision to Diff 62776.Jul 5 2016, 12:02 PM
arsenm retitled this revision from to AMDGPU: Use implicit_def for selecting anyext.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: kzhuravl, arsenm. · View Herald TranscriptJul 5 2016, 12:02 PM
• tstellarAMD accepted this revision.Jul 8 2016, 5:52 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Jul 8 2016, 5:52 PM
arsenm closed this revision.Jul 26 2016, 4:14 PM

r276819

Revision Contents

PathSize
lib/
Target/
AMDGPU/
11 lines

Diff 62776

lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 3,371 Lines • ▼ Show 20 Linesdef : Pat <
(S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16 (S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16
>; >;
def : Pat < def : Pat <
(i64 (sext_inreg i64:$src, i32)), (i64 (sext_inreg i64:$src, i32)),
(S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16 (S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16
>; >;
class ZExt_i64_i32_Pat <SDNode ext> : Pat < def : Pat <
(i64 (ext i32:$src)), (i64 (zext i32:$src)),
(REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1) (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
>; >;
def : Pat <
(i64 (anyext i32:$src)),
(REG_SEQUENCE SReg_64, $src, sub0, (i32 (IMPLICIT_DEF)), sub1)
>;
class ZExt_i64_i1_Pat <SDNode ext> : Pat < class ZExt_i64_i1_Pat <SDNode ext> : Pat <
(i64 (ext i1:$src)), (i64 (ext i1:$src)),
(REG_SEQUENCE VReg_64, (REG_SEQUENCE VReg_64,
(V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0, (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0,
(S_MOV_B32 0), sub1) (S_MOV_B32 0), sub1)
>; >;
def : ZExt_i64_i32_Pat<zext>;
def : ZExt_i64_i32_Pat<anyext>;
def : ZExt_i64_i1_Pat<zext>; def : ZExt_i64_i1_Pat<zext>;
def : ZExt_i64_i1_Pat<anyext>; def : ZExt_i64_i1_Pat<anyext>;
// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that // FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that
// REG_SEQUENCE patterns don't support instructions with multiple outputs. // REG_SEQUENCE patterns don't support instructions with multiple outputs.
def : Pat < def : Pat <
(i64 (sext i32:$src)), (i64 (sext i32:$src)),
(REG_SEQUENCE SReg_64, $src, sub0, (REG_SEQUENCE SReg_64, $src, sub0,
▲ Show 20 Lines • Show All 168 Lines • Show Last 20 Lines