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Differential D21689

[mips] Optimize materialization of i64 constants
ClosedPublic

Authored by sdardis on Jun 24 2016, 8:57 AM.

Details

Reviewers
dsanders
vkalintiris
Summary

Avoid MipsAnalyzeImmediate usage if the constant fits in an 32-bit
integer. This allows us to generate the same instructions for the
materialization of the same constants regardless the width of their
type.

Patch by: Vasileios Kalintiris

Contributions by: Simon Dardis

Diff Detail

Event Timeline

sdardis updated this revision to Diff 61802.Jun 24 2016, 8:57 AM
sdardis retitled this revision from to [mips] Optimize materialization of i64 constants.
sdardis updated this object.
sdardis added a reviewer: dsanders.
sdardis set the repository for this revision to rL LLVM.
sdardis added a subscriber: llvm-commits.
Herald added a reviewer: vkalintiris. · View Herald TranscriptJun 24 2016, 8:57 AM
Herald added subscribers: sdardis, dsanders. · View Herald Transcript
sdardis added a comment.Jul 22 2016, 2:25 AM

Ping.

dsanders accepted this revision.Jul 22 2016, 3:41 AM
dsanders edited edge metadata.

LGTM with an indentation nit

lib/Target/Mips/MipsInstrInfo.td
2463

Indentation

This revision is now accepted and ready to land.Jul 22 2016, 3:41 AM
sdardis closed this revision.Jul 25 2016, 3:58 AM

Thanks, committed rL276628.

Revision Contents

PathSize
lib/
Target/
Mips/
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6 lines
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39 lines
4 lines
test/
CodeGen/
Mips/
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llvm-ir/
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66 lines
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Diff 61802

lib/Target/Mips/MicroMips64r6InstrInfo.td

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def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6; def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6; def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6; def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
// Carry pattern // Carry pattern
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
(DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6; (DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
let AdditionalPredicates = [InMicroMips] in
defm : MaterializeImms<i64, ZERO_64, DADDIU_MM64R6, LUi64, ORi64>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction aliases // Instruction aliases
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsInstAlias<"dmtc0 $rt, $rd", def : MipsInstAlias<"dmtc0 $rt, $rd",
(DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
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lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 983 Lines • ▼ Show 20 Lineslet DecoderNamespace = "MicroMips" in {
def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>, def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6; RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MicroMips arbitrary patterns that map to one or more instructions // MicroMips arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsPat<(i32 immLi16:$imm),
(LI16_MM immLi16:$imm)>;
let AdditionalPredicates = [InMicroMips] in
defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>;
let Predicates = [InMicroMips] in { let Predicates = [InMicroMips] in {
def : MipsPat<(i32 immLi16:$imm), def : MipsPat<(i32 immLi16:$imm),
(LI16_MM immLi16:$imm)>; (LI16_MM immLi16:$imm)>;
def : MipsPat<(i32 immSExt16:$imm), def : MipsPat<(i32 immSExt16:$imm),
(ADDiu_MM ZERO, immSExt16:$imm)>; (ADDiu_MM ZERO, immSExt16:$imm)>;
def : MipsPat<(i32 immZExt16:$imm), def : MipsPat<(i32 immZExt16:$imm),
(ORi_MM ZERO, immZExt16:$imm)>; (ORi_MM ZERO, immZExt16:$imm)>;
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lib/Target/Mips/Mips64InstrInfo.td

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def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, MFC3OP_FM<0x12, 5>, def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, MFC3OP_FM<0x12, 5>,
ISA_MIPS3; ISA_MIPS3;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions // Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Materialize i64 constants.
defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>;
def : MipsPat<(i64 immZExt32Low16Zero:$imm),
(DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>;
def : MipsPat<(i64 immZExt32:$imm),
(ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16),
(LO16 imm:$imm))>;
// extended loads // extended loads
def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
// hi/lo relocs // hi/lo relocs
def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
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lib/Target/Mips/MipsInstrInfo.td

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def immZExt16 : PatLeaf<(imm), [{ def immZExt16 : PatLeaf<(imm), [{
if (N->getValueType(0) == MVT::i32) if (N->getValueType(0) == MVT::i32)
return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
else else
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
}], LO16>; }], LO16>;
// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
def immLow16Zero : PatLeaf<(imm), [{ def immSExt32Low16Zero : PatLeaf<(imm), [{
int64_t Val = N->getSExtValue(); int64_t Val = N->getSExtValue();
return isInt<32>(Val) && !(Val & 0xffff); return isInt<32>(Val) && !(Val & 0xffff);
}]>; }]>;
// Zero-extended 32-bit unsigned int with lower 16-bit cleared.
def immZExt32Low16Zero : PatLeaf<(imm), [{
uint64_t Val = N->getZExtValue();
return isUInt<32>(Val) && !(Val & 0xffff);
}]>;
// Note immediate fits as a 32 bit signed extended on target immediate.
def immSExt32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>;
// Note immediate fits as a 32 bit zero extended on target immediate.
def immZExt32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
// shamt field must fit in 5 bits. // shamt field must fit in 5 bits.
def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
def immZExt5Plus1 : PatLeaf<(imm), [{ def immZExt5Plus1 : PatLeaf<(imm), [{
return isUInt<5>(N->getZExtValue() - 1); return isUInt<5>(N->getZExtValue() - 1);
}]>; }]>;
def immZExt5Plus32 : PatLeaf<(imm), [{ def immZExt5Plus32 : PatLeaf<(imm), [{
return isUInt<5>(N->getZExtValue() - 32); return isUInt<5>(N->getZExtValue() - 32);
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// Load/store pattern templates. // Load/store pattern templates.
class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
// Materialize constants.
multiclass MaterializeImms<ValueType VT, Register ZEROReg,
Instruction ADDiuOp, Instruction LUiOp,
Instruction ORiOp> {
// Small immediates // Small immediates
let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>;
def : MipsPat<(i32 immSExt16:$in), def : MipsPat<(VT immZExt16:$imm), (ORiOp ZEROReg, imm:$imm)>;
(ADDiu ZERO, imm:$in)>;
def : MipsPat<(i32 immZExt16:$in), // Bits 32-16 set, sign/zero extended.
(ORi ZERO, imm:$in)>; def : MipsPat<(VT immSExt32Low16Zero:$imm), (LUiOp (HI16 imm:$imm))>;
}
def : MipsPat<(i32 immLow16Zero:$in),
(LUi (HI16 imm:$in))>;
// Arbitrary immediates // Arbitrary immediates
def : MipsPat<(i32 imm:$imm), def : MipsPat<(VT immSExt32:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; }
let AdditionalPredicates = [NotInMicroMips] in
defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>;
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// Carry MipsPatterns // Carry MipsPatterns
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
(SUBu GPR32:$lhs, GPR32:$rhs)>; (SUBu GPR32:$lhs, GPR32:$rhs)>;
} }
def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
(ADDu GPR32:$lhs, GPR32:$rhs)>, ASE_NOT_DSP; (ADDu GPR32:$lhs, GPR32:$rhs)>, ASE_NOT_DSP;
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lib/Target/Mips/MipsSEISelDAGToDAG.cpp

Show First 20 Lines • Show All 741 Lines • ▼ Show 20 Lines if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
} }
return true; return true;
} }
break; break;
} }
case ISD::Constant: { case ISD::Constant: {
const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node); const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
int64_t Imm = CN->getSExtValue();
unsigned Size = CN->getValueSizeInBits(0); unsigned Size = CN->getValueSizeInBits(0);
if (Size == 32) if (isInt<32>(Imm))
break; break;
MipsAnalyzeImmediate AnalyzeImm; MipsAnalyzeImmediate AnalyzeImm;
int64_t Imm = CN->getSExtValue();
const MipsAnalyzeImmediate::InstSeq &Seq = const MipsAnalyzeImmediate::InstSeq &Seq =
AnalyzeImm.Analyze(Imm, Size, false); AnalyzeImm.Analyze(Imm, Size, false);
MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
SDLoc DL(CN); SDLoc DL(CN);
SDNode *RegOpnd; SDNode *RegOpnd;
SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
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test/CodeGen/Mips/cmov.ll

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; FIXME: The 32-bit versions of this test are too complicated to reasonably ; FIXME: The 32-bit versions of this test are too complicated to reasonably
; match at the moment. They do show some missing optimizations though ; match at the moment. They do show some missing optimizations though
; such as: ; such as:
; (movz $a, $b, (neg $c)) -> (movn $a, $b, $c) ; (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)
; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 ; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5
; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4 ; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4
; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766
; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4
; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]
; 64-CMP-DAG: daddiu $[[I4:[0-9]+]], $zero, 4
; 64-CMP-DAG: daddiu $[[I5:2]], $zero, 5 ; 64-CMOV-DAG: lui $[[R1:[0-9]+]], 65535
; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766 ; 64-CMOV-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766
; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 ; 64-CMOV-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4
; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R3]]
; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5
; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4
; 64-CMP-DAG: lui $[[R1:[0-9]+]], 65535
; 64-CMP-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766
; 64-CMP-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4
; FIXME: We can do better than this by using selccz to choose between -0 and -2 ; FIXME: We can do better than this by using selccz to choose between -0 and -2
; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[R0]] ; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R3]]
; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]] ; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R3]]
; 64-CMP-DAG: or $2, $[[T1]], $[[T0]] ; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]
define i64 @slti64_3(i64 %a) { define i64 @slti64_3(i64 %a) {
entry: entry:
%cmp = icmp sgt i64 %a, -32770 %cmp = icmp sgt i64 %a, -32770
%conv = select i1 %cmp, i64 5, i64 4 %conv = select i1 %cmp, i64 5, i64 4
ret i64 %conv ret i64 %conv
} }
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test/CodeGen/Mips/fcmp.ll

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; 32-C: addiu $2, $zero, 0 ; 32-C: addiu $2, $zero, 0
; 32-CMP: addiu $2, $zero, 0 ; 32-CMP: addiu $2, $zero, 0
; 64-C: addiu $2, $zero, 0 ; 64-C: addiu $2, $zero, 0
; 64-CMP: addiu $2, $zero, 0 ; 64-CMP: addiu $2, $zero, 0
; MM-DAG: lui $2, 0 ; MM-DAG: li16 $2, 0
%1 = fcmp false float %a, %b %1 = fcmp false float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @oeq_f32(float %a, float %b) nounwind { define i32 @oeq_f32(float %a, float %b) nounwind {
; ALL-LABEL: oeq_f32: ; ALL-LABEL: oeq_f32:
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; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14 ; MM32R3-DAG: c.eq.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
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; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14 ; MM32R3-DAG: c.ule.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
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; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14 ; MM32R3-DAG: c.ult.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
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; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14 ; MM32R3-DAG: c.olt.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14 ; MM32R3-DAG: c.ole.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 19 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14 ; MM32R3-DAG: c.ueq.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
Show All 20 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14 ; MM32R3-DAG: c.un.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
Show All 18 Lines
; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14 ; MM32R3-DAG: c.ueq.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14 ; MM32R3-DAG: c.ole.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14 ; MM32R3-DAG: c.olt.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14 ; MM32R3-DAG: c.ult.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14 ; MM32R3-DAG: c.ule.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 19 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14 ; MM32R3-DAG: c.eq.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
Show All 18 Lines
; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14 ; MM32R3-DAG: c.un.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 25 Lines
; 32-C: addiu $2, $zero, 0 ; 32-C: addiu $2, $zero, 0
; 32-CMP: addiu $2, $zero, 0 ; 32-CMP: addiu $2, $zero, 0
; 64-C: addiu $2, $zero, 0 ; 64-C: addiu $2, $zero, 0
; 64-CMP: addiu $2, $zero, 0 ; 64-CMP: addiu $2, $zero, 0
; MM-DAG: lui $2, 0 ; MM-DAG: li16 $2, 0
%1 = fcmp false double %a, %b %1 = fcmp false double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @oeq_f64(double %a, double %b) nounwind { define i32 @oeq_f64(double %a, double %b) nounwind {
; ALL-LABEL: oeq_f64: ; ALL-LABEL: oeq_f64:
Show All 9 Lines
; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14 ; MM32R3-DAG: c.eq.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14 ; MM32R3-DAG: c.ule.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14 ; MM32R3-DAG: c.ult.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14 ; MM32R3-DAG: c.olt.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14 ; MM32R3-DAG: c.ole.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 19 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14 ; MM32R3-DAG: c.ueq.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
Show All 20 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14 ; MM32R3-DAG: c.un.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
Show All 18 Lines
; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14 ; MM32R3-DAG: c.ueq.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14 ; MM32R3-DAG: c.ole.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14 ; MM32R3-DAG: c.olt.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14 ; MM32R3-DAG: c.ult.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 17 Lines
; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14 ; MM32R3-DAG: c.ule.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
Show All 19 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14 ; MM32R3-DAG: c.eq.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
Show All 18 Lines
; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 ; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14 ; MM32R3-DAG: c.un.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
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test/CodeGen/Mips/llvm-ir/add.ll

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Lines; ALL-LABEL: add_i128_4:
; GP64: daddiu $[[T1:[0-9]+]], $zero, 4 ; GP64: daddiu $[[T1:[0-9]+]], $zero, 4
; GP64: sltu $[[T1]], $[[T0]], $[[T1]] ; GP64: sltu $[[T1]], $[[T0]], $[[T1]]
; GP64: daddu $2, $4, $[[T1]] ; GP64: daddu $2, $4, $[[T1]]
; MM32: addiu $[[T0:[0-9]+]], $7, 4 ; MM32: addiu $[[T0:[0-9]+]], $7, 4
; MM32: li16 $[[T1:[0-9]+]], 4 ; MM32: li16 $[[T1:[0-9]+]], 4
; MM32: sltu $[[T1]], $[[T0]], $[[T1]] ; MM32: sltu $[[T1]], $[[T0]], $[[T1]]
; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]]
; MM32: lui $[[T1]], 0 ; MM32: li16 $[[T1]], 0
; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]] ; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; MM32: addu $[[T3]], $5, $[[T3]] ; MM32: addu $[[T3]], $5, $[[T3]]
; MM32: sltu $[[T1]], $[[T3]], $[[T1]] ; MM32: sltu $[[T1]], $[[T3]], $[[T1]]
; MM32: addu $[[T1]], $4, $[[T1]] ; MM32: addu $[[T1]], $4, $[[T1]]
; MM32: move $4, $[[T2]] ; MM32: move $4, $[[T2]]
; MM32: move $5, $[[T0]] ; MM32: move $5, $[[T0]]
; MM64: daddiu $[[T0:[0-9]+]], $5, 4 ; MM64: daddiu $[[T0:[0-9]+]], $5, 4
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines; ALL-LABEL: add_i128_3:
; GP64: daddiu $[[T1:[0-9]+]], $zero, 3 ; GP64: daddiu $[[T1:[0-9]+]], $zero, 3
; GP64: sltu $[[T1]], $[[T0]], $[[T1]] ; GP64: sltu $[[T1]], $[[T0]], $[[T1]]
; GP64: daddu $2, $4, $[[T1]] ; GP64: daddu $2, $4, $[[T1]]
; MM32: addiu $[[T0:[0-9]+]], $7, 3 ; MM32: addiu $[[T0:[0-9]+]], $7, 3
; MM32: li16 $[[T1:[0-9]+]], 3 ; MM32: li16 $[[T1:[0-9]+]], 3
; MM32: sltu $[[T1]], $[[T0]], $[[T1]] ; MM32: sltu $[[T1]], $[[T0]], $[[T1]]
; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]]
; MM32: lui $[[T3:[0-9]+]], 0 ; MM32: li16 $[[T3:[0-9]+]], 0
; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
; MM32: addu $[[T4]], $5, $[[T4]] ; MM32: addu $[[T4]], $5, $[[T4]]
; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]] ; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]]
; MM32: addu $[[T5]], $4, $[[T5]] ; MM32: addu $[[T5]], $4, $[[T5]]
; MM32: move $4, $[[T2]] ; MM32: move $4, $[[T2]]
; MM32: move $5, $[[T0]] ; MM32: move $5, $[[T0]]
; MM64: daddiu $[[T0:[0-9]+]], $5, 3 ; MM64: daddiu $[[T0:[0-9]+]], $5, 3
; MM64: daddiu $[[T1:[0-9]+]], $zero, 3 ; MM64: daddiu $[[T1:[0-9]+]], $zero, 3
; MM64: sltu $[[T1]], $[[T0]], $[[T1]] ; MM64: sltu $[[T1]], $[[T0]], $[[T1]]
; MM64: daddu $2, $4, $[[T1]] ; MM64: daddu $2, $4, $[[T1]]
%r = add i128 3, %a %r = add i128 3, %a
ret i128 %r ret i128 %r
} }

test/CodeGen/Mips/llvm-ir/and.ll

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
define signext i1 @and_i1_4(i1 signext %b) { define signext i1 @and_i1_4(i1 signext %b) {
entry: entry:
; ALL-LABEL: and_i1_4: ; ALL-LABEL: and_i1_4:
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: addiu $2, $zero, 0 ; GP64: addiu $2, $zero, 0
; MM: lui $2, 0 ; MM: li16 $2, 0
%r = and i1 4, %b %r = and i1 4, %b
ret i1 %r ret i1 %r
} }
define signext i8 @and_i8_4(i8 signext %b) { define signext i8 @and_i8_4(i8 signext %b) {
entry: entry:
; ALL-LABEL: and_i8_4: ; ALL-LABEL: and_i8_4:
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; ALL-LABEL: and_i64_4: ; ALL-LABEL: and_i64_4:
; GP32: andi $3, $5, 4 ; GP32: andi $3, $5, 4
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: andi $2, $4, 4 ; GP64: andi $2, $4, 4
; MM32: andi16 $3, $5, 4 ; MM32: andi16 $3, $5, 4
; MM32: lui $2, 0 ; MM32: li16 $2, 0
; MM64: andi $2, $4, 4 ; MM64: andi $2, $4, 4
%r = and i64 4, %b %r = and i64 4, %b
ret i64 %r ret i64 %r
} }
define signext i128 @and_i128_4(i128 signext %b) { define signext i128 @and_i128_4(i128 signext %b) {
entry: entry:
; ALL-LABEL: and_i128_4: ; ALL-LABEL: and_i128_4:
; GP32: andi $5, $7, 4 ; GP32: andi $5, $7, 4
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP32: addiu $3, $zero, 0 ; GP32: addiu $3, $zero, 0
; GP32: addiu $4, $zero, 0 ; GP32: addiu $4, $zero, 0
; GP64: andi $3, $5, 4 ; GP64: andi $3, $5, 4
; GP64: daddiu $2, $zero, 0 ; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 4 ; MM32: andi16 $5, $7, 4
; MM32: lui $2, 0 ; MM32: li16 $2, 0
; MM32: lui $3, 0 ; MM32: li16 $3, 0
; MM32: lui $4, 0 ; MM32: li16 $4, 0
; MM64: andi $3, $5, 4 ; MM64: andi $3, $5, 4
; MM64: daddiu $2, $zero, 0 ; MM64: daddiu $2, $zero, 0
%r = and i128 4, %b %r = and i128 4, %b
ret i128 %r ret i128 %r
} }
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; ALL-LABEL: and_i64_31: ; ALL-LABEL: and_i64_31:
; GP32: andi $3, $5, 31 ; GP32: andi $3, $5, 31
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: andi $2, $4, 31 ; GP64: andi $2, $4, 31
; MM32: andi16 $3, $5, 31 ; MM32: andi16 $3, $5, 31
; MM32: lui $2, 0 ; MM32: li16 $2, 0
; MM64: andi $2, $4, 31 ; MM64: andi $2, $4, 31
%r = and i64 31, %b %r = and i64 31, %b
ret i64 %r ret i64 %r
} }
define signext i128 @and_i128_31(i128 signext %b) { define signext i128 @and_i128_31(i128 signext %b) {
entry: entry:
; ALL-LABEL: and_i128_31: ; ALL-LABEL: and_i128_31:
; GP32: andi $5, $7, 31 ; GP32: andi $5, $7, 31
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP32: addiu $3, $zero, 0 ; GP32: addiu $3, $zero, 0
; GP32: addiu $4, $zero, 0 ; GP32: addiu $4, $zero, 0
; GP64: andi $3, $5, 31 ; GP64: andi $3, $5, 31
; GP64: daddiu $2, $zero, 0 ; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 31 ; MM32: andi16 $5, $7, 31
; MM32: lui $2, 0 ; MM32: li16 $2, 0
; MM32: lui $3, 0 ; MM32: li16 $3, 0
; MM32: lui $4, 0 ; MM32: li16 $4, 0
; MM64: andi $3, $5, 31 ; MM64: andi $3, $5, 31
; MM64: daddiu $2, $zero, 0 ; MM64: daddiu $2, $zero, 0
%r = and i128 31, %b %r = and i128 31, %b
ret i128 %r ret i128 %r
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; ALL-LABEL: and_i64_255: ; ALL-LABEL: and_i64_255:
; GP32: andi $3, $5, 255 ; GP32: andi $3, $5, 255
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: andi $2, $4, 255 ; GP64: andi $2, $4, 255
; MM32: andi16 $3, $5, 255 ; MM32: andi16 $3, $5, 255
; MM32: lui $2, 0 ; MM32: li16 $2, 0
; MM64: andi $2, $4, 255 ; MM64: andi $2, $4, 255
%r = and i64 255, %b %r = and i64 255, %b
ret i64 %r ret i64 %r
} }
define signext i128 @and_i128_255(i128 signext %b) { define signext i128 @and_i128_255(i128 signext %b) {
entry: entry:
; ALL-LABEL: and_i128_255: ; ALL-LABEL: and_i128_255:
; GP32: andi $5, $7, 255 ; GP32: andi $5, $7, 255
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP32: addiu $3, $zero, 0 ; GP32: addiu $3, $zero, 0
; GP32: addiu $4, $zero, 0 ; GP32: addiu $4, $zero, 0
; GP64: andi $3, $5, 255 ; GP64: andi $3, $5, 255
; GP64: daddiu $2, $zero, 0 ; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 255 ; MM32: andi16 $5, $7, 255
; MM32: lui $2, 0 ; MM32: li16 $2, 0
; MM32: lui $3, 0 ; MM32: li16 $3, 0
; MM32: lui $4, 0 ; MM32: li16 $4, 0
; MM64: andi $3, $5, 255 ; MM64: andi $3, $5, 255
; MM64: daddiu $2, $zero, 0 ; MM64: daddiu $2, $zero, 0
%r = and i128 255, %b %r = and i128 255, %b
ret i128 %r ret i128 %r
} }
define signext i1 @and_i1_32768(i1 signext %b) { define signext i1 @and_i1_32768(i1 signext %b) {
entry: entry:
; ALL-LABEL: and_i1_32768: ; ALL-LABEL: and_i1_32768:
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: addiu $2, $zero, 0 ; GP64: addiu $2, $zero, 0
; MM: lui $2, 0 ; MM: li16 $2, 0
%r = and i1 32768, %b %r = and i1 32768, %b
ret i1 %r ret i1 %r
} }
define signext i8 @and_i8_32768(i8 signext %b) { define signext i8 @and_i8_32768(i8 signext %b) {
entry: entry:
; ALL-LABEL: and_i8_32768: ; ALL-LABEL: and_i8_32768:
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: addiu $2, $zero, 0 ; GP64: addiu $2, $zero, 0
; MM: lui $2, 0 ; MM: li16 $2, 0
%r = and i8 32768, %b %r = and i8 32768, %b
ret i8 %r ret i8 %r
} }
define signext i16 @and_i16_32768(i16 signext %b) { define signext i16 @and_i16_32768(i16 signext %b) {
entry: entry:
; ALL-LABEL: and_i16_32768: ; ALL-LABEL: and_i16_32768:
Show All 30 Lines
; ALL-LABEL: and_i64_32768: ; ALL-LABEL: and_i64_32768:
; GP32: andi $3, $5, 32768 ; GP32: andi $3, $5, 32768
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: andi $2, $4, 32768 ; GP64: andi $2, $4, 32768
; MM32: andi16 $3, $5, 32768 ; MM32: andi16 $3, $5, 32768
; MM32: lui $2, 0 ; MM32: li16 $2, 0
; MM64: andi $2, $4, 32768 ; MM64: andi $2, $4, 32768
%r = and i64 32768, %b %r = and i64 32768, %b
ret i64 %r ret i64 %r
} }
define signext i128 @and_i128_32768(i128 signext %b) { define signext i128 @and_i128_32768(i128 signext %b) {
entry: entry:
; ALL-LABEL: and_i128_32768: ; ALL-LABEL: and_i128_32768:
; GP32: andi $5, $7, 32768 ; GP32: andi $5, $7, 32768
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP32: addiu $3, $zero, 0 ; GP32: addiu $3, $zero, 0
; GP32: addiu $4, $zero, 0 ; GP32: addiu $4, $zero, 0
; GP64: andi $3, $5, 32768 ; GP64: andi $3, $5, 32768
; GP64: daddiu $2, $zero, 0 ; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 32768 ; MM32: andi16 $5, $7, 32768
; MM32: lui $2, 0 ; MM32: li16 $2, 0
; MM32: lui $3, 0 ; MM32: li16 $3, 0
; MM32: lui $4, 0 ; MM32: li16 $4, 0
; MM64: andi $3, $5, 32768 ; MM64: andi $3, $5, 32768
; MM64: daddiu $2, $zero, 0 ; MM64: daddiu $2, $zero, 0
%r = and i128 32768, %b %r = and i128 32768, %b
ret i128 %r ret i128 %r
} }
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entry: entry:
; ALL-LABEL: and_i64_65: ; ALL-LABEL: and_i64_65:
; GP32: andi $3, $5, 65 ; GP32: andi $3, $5, 65
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: andi $2, $4, 65 ; GP64: andi $2, $4, 65
; MM32: andi $3, $5, 65 ; MM32-DAG: andi $3, $5, 65
; MM32: lui $2, 0 ; MM32-DAG: li16 $2, 0
; MM64: andi $2, $4, 65 ; MM64: andi $2, $4, 65
%r = and i64 65, %b %r = and i64 65, %b
ret i64 %r ret i64 %r
} }
define signext i128 @and_i128_65(i128 signext %b) { define signext i128 @and_i128_65(i128 signext %b) {
entry: entry:
; ALL-LABEL: and_i128_65: ; ALL-LABEL: and_i128_65:
; GP32: andi $5, $7, 65 ; GP32: andi $5, $7, 65
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP32: addiu $3, $zero, 0 ; GP32: addiu $3, $zero, 0
; GP32: addiu $4, $zero, 0 ; GP32: addiu $4, $zero, 0
; GP64: andi $3, $5, 65 ; GP64: andi $3, $5, 65
; GP64: daddiu $2, $zero, 0 ; GP64: daddiu $2, $zero, 0
; MM32: andi $5, $7, 65 ; MM32-DAG: andi $5, $7, 65
; MM32: lui $2, 0 ; MM32-DAG: li16 $2, 0
; MM32: lui $3, 0 ; MM32-DAG: li16 $3, 0
; MM32: lui $4, 0 ; MM32-DAG: li16 $4, 0
; MM64: andi $3, $5, 65 ; MM64: andi $3, $5, 65
; MM64: daddiu $2, $zero, 0 ; MM64: daddiu $2, $zero, 0
%r = and i128 65, %b %r = and i128 65, %b
ret i128 %r ret i128 %r
} }
define signext i1 @and_i1_256(i1 signext %b) { define signext i1 @and_i1_256(i1 signext %b) {
entry: entry:
; ALL-LABEL: and_i1_256: ; ALL-LABEL: and_i1_256:
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: addiu $2, $zero, 0 ; GP64: addiu $2, $zero, 0
; MM: lui $2, 0 ; MM: li16 $2, 0
%r = and i1 256, %b %r = and i1 256, %b
ret i1 %r ret i1 %r
} }
define signext i8 @and_i8_256(i8 signext %b) { define signext i8 @and_i8_256(i8 signext %b) {
entry: entry:
; ALL-LABEL: and_i8_256: ; ALL-LABEL: and_i8_256:
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: addiu $2, $zero, 0 ; GP64: addiu $2, $zero, 0
; MM: lui $2, 0 ; MM: li16 $2, 0
%r = and i8 256, %b %r = and i8 256, %b
ret i8 %r ret i8 %r
} }
define signext i16 @and_i16_256(i16 signext %b) { define signext i16 @and_i16_256(i16 signext %b) {
entry: entry:
; ALL-LABEL: and_i16_256: ; ALL-LABEL: and_i16_256:
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entry: entry:
; ALL-LABEL: and_i64_256: ; ALL-LABEL: and_i64_256:
; GP32: andi $3, $5, 256 ; GP32: andi $3, $5, 256
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP64: andi $2, $4, 256 ; GP64: andi $2, $4, 256
; MM32: andi $3, $5, 256 ; MM32-DAG: andi $3, $5, 256
; MM32: lui $2, 0 ; MM32-DAG: li16 $2, 0
; MM64: andi $2, $4, 256 ; MM64: andi $2, $4, 256
%r = and i64 256, %b %r = and i64 256, %b
ret i64 %r ret i64 %r
} }
define signext i128 @and_i128_256(i128 signext %b) { define signext i128 @and_i128_256(i128 signext %b) {
entry: entry:
; ALL-LABEL: and_i128_256: ; ALL-LABEL: and_i128_256:
; GP32: andi $5, $7, 256 ; GP32: andi $5, $7, 256
; GP32: addiu $2, $zero, 0 ; GP32: addiu $2, $zero, 0
; GP32: addiu $3, $zero, 0 ; GP32: addiu $3, $zero, 0
; GP32: addiu $4, $zero, 0 ; GP32: addiu $4, $zero, 0
; GP64: andi $3, $5, 256 ; GP64: andi $3, $5, 256
; GP64: daddiu $2, $zero, 0 ; GP64: daddiu $2, $zero, 0
; MM32: andi $5, $7, 256 ; MM32-DAG: andi $5, $7, 256
; MM32: lui $2, 0 ; MM32-DAG: li16 $2, 0
; MM32: lui $3, 0 ; MM32-DAG: li16 $3, 0
; MM32: lui $4, 0 ; MM32-DAG: li16 $4, 0
; MM64: andi $3, $5, 256 ; MM64: andi $3, $5, 256
; MM64: daddiu $2, $zero, 0 ; MM64: daddiu $2, $zero, 0
%r = and i128 256, %b %r = and i128 256, %b
ret i128 %r ret i128 %r
} }

test/CodeGen/Mips/llvm-ir/lshr.ll

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines; ALL-LABEL: lshr_i64:
; MMR3: srlv $[[T0:[0-9]+]], $5, $7 ; MMR3: srlv $[[T0:[0-9]+]], $5, $7
; MMR3: sll16 $[[T1:[0-9]+]], $4, 1 ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1
; MMR3: not16 $[[T2:[0-9]+]], $7 ; MMR3: not16 $[[T2:[0-9]+]], $7
; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
; MMR3: srlv $[[T5:[0-9]+]], $4, $7 ; MMR3: srlv $[[T5:[0-9]+]], $4, $7
; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; MMR3: lui $[[T8:[0-9]+]], 0 ; MMR3: li16 $[[T8:[0-9]+]], 0
; MMR3: movn $2, $[[T8]], $[[T6]] ; MMR3: movn $2, $[[T8]], $[[T6]]
; MMR6: srlv $[[T0:[0-9]+]], $5, $7 ; MMR6: srlv $[[T0:[0-9]+]], $5, $7
; MMR6: sll16 $[[T1:[0-9]+]], $4, 1 ; MMR6: sll16 $[[T1:[0-9]+]], $4, 1
; MMR6: not16 $[[T2:[0-9]+]], $7 ; MMR6: not16 $[[T2:[0-9]+]], $7
; MMR6: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] ; MMR6: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]]
; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32
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test/CodeGen/Mips/llvm-ir/ret.ll

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
define i64 @ret_i64_65537() { define i64 @ret_i64_65537() {
; ALL-LABEL: ret_i64_65537: ; ALL-LABEL: ret_i64_65537:
; ALL: lui $[[T0:[0-9]+]], 1 ; ALL: lui $[[T0:[0-9]+]], 1
; GPR32-DAG: ori $3, $[[T0]], 1 ; GPR32-DAG: ori $3, $[[T0]], 1
; GPR32-DAG: addiu $2, $zero, 0 ; GPR32-DAG: addiu $2, $zero, 0
; GPR64-DAG: daddiu $2, $[[T0]], 1 ; GPR64-DAG: ori $2, $[[T0]], 1
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
ret i64 65537 ret i64 65537
} }
define i64 @ret_i64_281479271677952() { define i64 @ret_i64_281479271677952() {
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test/CodeGen/Mips/llvm-ir/select-int.ll

Show First 20 Lines • Show All 253 Lines • ▼ Show 20 Linesdefine i8* @tst_select_word_cst(i8* %a, i8* %b) {
; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]] ; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]] ; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; FIXME: This shift is redundant. ; FIXME: This shift is redundant.
; SEL-64: sll $[[T2]], $[[T2]], 0 ; SEL-64: sll $[[T2]], $[[T2]], 0
; SEL-64: seleqz $2, $4, $[[T2]] ; SEL-64: seleqz $2, $4, $[[T2]]
; MM32R3: li16 $[[T0:[0-9]+]], -1 ; MM32R3: li16 $[[T0:[0-9]+]], -1
; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]] ; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]]
; MM32R3: lui $[[T2:[0-9]+]], 0 ; MM32R3: li16 $[[T2:[0-9]+]], 0
; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]] ; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; MM32R3: move $2, $[[T3]] ; MM32R3: move $2, $[[T3]]
; MM32R6: li16 $[[T0:[0-9]+]], -1 ; MM32R6: li16 $[[T0:[0-9]+]], -1
; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]] ; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]]
; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]] ; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; MM32R6: seleqz $2, $4, $[[T2]] ; MM32R6: seleqz $2, $4, $[[T2]]
%cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*) %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
%r = select i1 %cmp, i8* %a, i8* null %r = select i1 %cmp, i8* %a, i8* null
ret i8* %r ret i8* %r
} }

test/CodeGen/Mips/llvm-ir/shl.ll

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines; ALL-LABEL: shl_i64:
; MMR3: sllv $[[T0:[0-9]+]], $4, $7 ; MMR3: sllv $[[T0:[0-9]+]], $4, $7
; MMR3: srl16 $[[T1:[0-9]+]], $5, 1 ; MMR3: srl16 $[[T1:[0-9]+]], $5, 1
; MMR3: not16 $[[T2:[0-9]+]], $7 ; MMR3: not16 $[[T2:[0-9]+]], $7
; MMR3: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]] ; MMR3: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]]
; MMR3: sllv $[[T5:[0-9]+]], $5, $7 ; MMR3: sllv $[[T5:[0-9]+]], $5, $7
; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32
; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; MMR3: lui $[[T8:[0-9]+]], 0 ; MMR3: li16 $[[T8:[0-9]+]], 0
; MMR3: movn $3, $[[T8]], $[[T6]] ; MMR3: movn $3, $[[T8]], $[[T6]]
; MMR6: sllv $[[T0:[0-9]+]], $4, $7 ; MMR6: sllv $[[T0:[0-9]+]], $4, $7
; MMR6: srl16 $[[T1:[0-9]+]], $5, 1 ; MMR6: srl16 $[[T1:[0-9]+]], $5, 1
; MMR6: not16 $[[T2:[0-9]+]], $7 ; MMR6: not16 $[[T2:[0-9]+]], $7
; MMR6: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]] ; MMR6: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]]
; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]]
; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32
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test/CodeGen/Mips/mips64imm.ll

; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s ; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
define i32 @foo1() nounwind readnone { define i32 @foo1() nounwind readnone {
entry: entry:
; CHECK: foo1 ; CHECK: foo1
; CHECK: lui ${{[0-9]+}}, 4660 ; CHECK: lui ${{[0-9]+}}, 4660
; CHECK-NOT: ori ; CHECK-NOT: ori
ret i32 305397760 ret i32 305397760
} }
define i64 @foo3() nounwind readnone { define i64 @foo3() nounwind readnone {
entry: entry:
; CHECK: foo3 ; CHECK: foo3
; CHECK: lui $[[R0:[0-9]+]], 4660 ; CHECK: lui $[[R0:[0-9]+]], 4660
; CHECK: daddiu ${{[0-9]+}}, $[[R0]], 22136 ; CHECK: ori ${{[0-9]+}}, $[[R0]], 22136
ret i64 305419896 ret i64 305419896
} }
define i64 @foo6() nounwind readnone { define i64 @foo6() nounwind readnone {
entry: entry:
; CHECK: foo6 ; CHECK: foo6
; CHECK: ori ${{[0-9]+}}, $zero, 33332 ; CHECK: ori ${{[0-9]+}}, $zero, 33332
ret i64 33332 ret i64 33332
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