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Differential D21549

[ARM] Refactor Thumb2 mul instruction descriptions
ClosedPublic

Authored by samparker on Jun 21 2016, 2:16 AM.

Details

Reviewers
rengolin
Commits
rG06692203edf0: [ARM] Refactor Thumb2 mul instruction descs
rL274347: [ARM] Refactor Thumb2 mul instruction descs
Summary

No functional changes. Just created wrapper classes around the 3 and 4 reg mult and mac instruction classes.

Diff Detail

Repository
rL LLVM

Event Timeline

samparker updated this revision to Diff 61348.Jun 21 2016, 2:16 AM
samparker retitled this revision from to [ARM] Refactor Thumb2 mul instruction descriptions.
samparker updated this object.
Herald added subscribers: rengolin, aemerson. · View Herald TranscriptJun 21 2016, 2:16 AM
rengolin accepted this revision.Jun 28 2016, 5:04 AM
rengolin added a reviewer: rengolin.

Hi Sam,

Sorry it took so long, this is a complicated patch. :)

All in all, this is a great patch. Removes a lot of duplication and makes it less error prone. Thanks for doing this work.

I couldn't see anything wrong with it, though I may have missed in the huge list of changes. I'm assuming this passes all tests (internal and external), so, LGTM.

Thanks!
--renato

This revision is now accepted and ready to land.Jun 28 2016, 5:04 AM
Closed by commit rL274347: [ARM] Refactor Thumb2 mul instruction descs (authored by sam_parker). · Explain WhyJul 1 2016, 6:03 AM
This revision was automatically updated to reflect the committed changes.
samparker mentioned this in D21929: [ARM] Correct t2UMAAL Description.Jul 1 2016, 12:30 PM
samparker updated this revision to Diff 63478.Jul 11 2016, 2:16 AM
samparker edited edge metadata.
samparker removed rL LLVM as the repository for this revision.

Original commit was reverted due to the thumb umaal description being incorrect and there was no test case to catch it. Updated patch corrects the bug and adds testing for t2UMAAL

samparker added a comment.Jul 11 2016, 2:19 AM

Hi Renato,

Are you able to see the change clearly now? I'm not really sure how to use this interface so can't tell if you can see the incremental change.

cheers,
sam

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
ARM/
467 lines

Diff 62487

llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Show First 20 Lines • Show All 530 Lines • ▼ Show 20 Linesclass T2FourReg<dag oops, dag iops, InstrItinClass itin,
let Inst{19-16} = Rn; let Inst{19-16} = Rn;
let Inst{15-12} = Ra; let Inst{15-12} = Ra;
let Inst{11-8} = Rd; let Inst{11-8} = Rd;
let Inst{3-0} = Rm; let Inst{3-0} = Rm;
} }
class T2MulLong<bits<3> opc22_20, bits<4> opc7_4, class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
dag oops, dag iops, InstrItinClass itin, string opc, list<dag> pattern>
string opc, string asm, list<dag> pattern> : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
: T2I<oops, iops, itin, opc, asm, pattern> { opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern> {
bits<4> RdLo; bits<4> RdLo;
bits<4> RdHi; bits<4> RdHi;
bits<4> Rn; bits<4> Rn;
bits<4> Rm; bits<4> Rm;
let Inst{31-23} = 0b111110111; let Inst{31-23} = 0b111110111;
let Inst{22-20} = opc22_20; let Inst{22-20} = opc22_20;
let Inst{19-16} = Rn; let Inst{19-16} = Rn;
let Inst{15-12} = RdLo; let Inst{15-12} = RdLo;
let Inst{11-8} = RdHi; let Inst{11-8} = RdHi;
let Inst{7-4} = opc7_4; let Inst{7-4} = opc7_4;
let Inst{3-0} = Rm; let Inst{3-0} = Rm;
} }
class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>
dag oops, dag iops, InstrItinClass itin, : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
string opc, string asm, list<dag> pattern> (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
: T2I<oops, iops, itin, opc, asm, pattern> { opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi"> {
bits<4> RdLo; bits<4> RdLo;
bits<4> RdHi; bits<4> RdHi;
bits<4> Rn; bits<4> Rn;
bits<4> Rm; bits<4> Rm;
let Inst{31-23} = 0b111110111; let Inst{31-23} = 0b111110111;
let Inst{22-20} = opc22_20; let Inst{22-20} = opc22_20;
let Inst{19-16} = Rn; let Inst{19-16} = Rn;
▲ Show 20 Lines • Show All 1,972 Lines • ▼ Show 20 Linesdef t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
[(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> { [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000; let Inst{22-20} = 0b000;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-4} = 0b0000; // Multiply let Inst{7-4} = 0b0000; // Multiply
} }
def t2MLA: T2FourReg< class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern>
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"mla", "\t$Rd, $Rn, $Rm, $Ra", opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
[(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
Requires<[IsThumb2, UseMulOps]> { Requires<[IsThumb2, UseMulOps]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000; let Inst{22-20} = 0b000;
let Inst{7-4} = 0b0000; // Multiply let Inst{7-4} = op7_4;
} }
def t2MLS: T2FourReg< def t2MLA : T2FourRegMLA<0b0000, "mla",
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
"mls", "\t$Rd, $Rn, $Rm, $Ra", rGPR:$Ra))]>;
[(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>, def t2MLS: T2FourRegMLA<0b0001, "mls",
Requires<[IsThumb2, UseMulOps]> { [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
let Inst{31-27} = 0b11111; rGPR:$Rm)))]>;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000;
let Inst{7-4} = 0b0001; // Multiply and Subtract
}
// Extra precision multiplies with low / high results // Extra precision multiplies with low / high results
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let isCommutable = 1 in { let isCommutable = 1 in {
def t2SMULL : T2MulLong<0b000, 0b0000, def t2SMULL : T2MulLong<0b000, 0b0000, "smull", []>;
(outs rGPR:$RdLo, rGPR:$RdHi), def t2UMULL : T2MulLong<0b010, 0b0000, "umull", []>;
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
"smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
def t2UMULL : T2MulLong<0b010, 0b0000,
(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
"umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
} // isCommutable } // isCommutable
// Multiply + accumulate // Multiply + accumulate
def t2SMLAL : T2MlaLong<0b100, 0b0000, def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
(outs rGPR:$RdLo, rGPR:$RdHi), def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, def t2UMAAL : T2MulLong<0b110, 0b0110, "umaal", []>,
"smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
def t2UMLAL : T2MlaLong<0b110, 0b0000,
(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
"umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
def t2UMAAL : T2MulLong<0b110, 0b0110,
(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
"umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
Requires<[IsThumb2, HasDSP]>; Requires<[IsThumb2, HasDSP]>;
} // hasSideEffects } // hasSideEffects
// Rounding variants of the below included for disassembly only // Rounding variants of the below included for disassembly only
// Most significant word multiply // Most significant word multiply
def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern>
"smmul", "\t$Rd, $Rn, $Rm", : T2ThreeReg<(outs rGPR:$Rd),
[(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>, (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
Requires<[IsThumb2, HasDSP]> { opc, "\t$Rd, $Rn, $Rm", pattern>,
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
}
def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
"smmulr", "\t$Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]> { Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101; let Inst{22-20} = 0b101;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) let Inst{7-4} = op7_4;
}
def t2SMMLA : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"smmla", "\t$Rd, $Rn, $Rm, $Ra",
[(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101;
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
}
def t2SMMLAR: T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101;
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
} }
def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
rGPR:$Rm))]>;
def t2SMMULR : T2SMMUL<0b0001, "smmulr", []>;
def t2SMMLS: T2FourReg< class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, list<dag> pattern>
"smmls", "\t$Rd, $Rn, $Rm, $Ra", : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
[(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>, opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
Requires<[IsThumb2, HasDSP, UseMulOps]> { Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b110; let Inst{22-20} = op22_20;
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) let Inst{7-4} = op7_4;
}
def t2SMMLSR:T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b110;
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
}
multiclass T2I_smul<string opc, SDNode opnode> {
def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
(sext_inreg rGPR:$Rm, i16)))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00;
}
def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
(sra rGPR:$Rm, (i32 16))))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01;
}
def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
(sext_inreg rGPR:$Rm, i16)))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b10;
}
def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16))))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b11;
} }
def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
[]>, def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
Requires<[IsThumb2, HasDSP]> { def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls",
let Inst{31-27} = 0b11111; [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>;
let Inst{26-23} = 0b0110; def t2SMMLSR:T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
let Inst{22-20} = 0b011;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00;
}
def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", list<dag> pattern>
[]>, : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
"\t$Rd, $Rn, $Rm", pattern>,
Requires<[IsThumb2, HasDSP]> { Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011; let Inst{22-20} = op22_20;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00; let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01; let Inst{5-4} = op5_4;
} }
}
multiclass T2I_smla<string opc, SDNode opnode> { def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
def BB : T2FourReg< [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, (sext_inreg rGPR:$Rm, i16)))]>;
!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
[(set rGPR:$Rd, (add rGPR:$Ra, [(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16),
(opnode (sext_inreg rGPR:$Rn, i16), (sra rGPR:$Rm, (i32 16))))]>;
(sext_inreg rGPR:$Rm, i16))))]>, def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
Requires<[IsThumb2, HasDSP, UseMulOps]> { [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
let Inst{31-27} = 0b11111; (sext_inreg rGPR:$Rm, i16)))]>;
let Inst{26-23} = 0b0110; def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
let Inst{22-20} = 0b001; [(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
let Inst{7-6} = 0b00; (sra rGPR:$Rm, (i32 16))))]>;
let Inst{5-4} = 0b00; def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>;
} def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>;
def BT : T2FourReg< class T2FourRegSMLA<bits<2> op5_4, string opc, list<dag> pattern>
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
(sra rGPR:$Rm, (i32 16)))))]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> { Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001; let Inst{22-20} = 0b001;
let Inst{7-6} = 0b00; let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01; let Inst{5-4} = op5_4;
} }
def TB : T2FourReg< def t2SMLABB : T2FourRegSMLA<0b00, "smlabb",
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, [(set rGPR:$Rd, (add rGPR:$Ra,
!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", (mul (sext_inreg rGPR:$Rn, i16),
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), (sext_inreg rGPR:$Rm, i16))))]>;
(sext_inreg rGPR:$Rm, i16))))]>, def t2SMLABT : T2FourRegSMLA<0b01, "smlabt",
Requires<[IsThumb2, HasDSP, UseMulOps]> { [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16),
let Inst{31-27} = 0b11111; (sra rGPR:$Rm, (i32 16)))))]>;
let Inst{26-23} = 0b0110; def t2SMLATB : T2FourRegSMLA<0b10, "smlatb",
let Inst{22-20} = 0b001; [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
let Inst{7-6} = 0b00; (sext_inreg rGPR:$Rm, i16))))]>;
let Inst{5-4} = 0b10; def t2SMLATT : T2FourRegSMLA<0b11, "smlatt",
} [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16)))))]>;
def TT : T2FourReg< def t2SMLAWB : T2FourRegSMLA<0b00, "smlawb", []> {
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16)))))]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b11;
}
def WB : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
[]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011; let Inst{22-20} = 0b011;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00;
} }
def t2SMLAWT : T2FourRegSMLA<0b01, "smlawt", []> {
def WT : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
[]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011; let Inst{22-20} = 0b011;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01;
}
} }
defm t2SMUL : T2I_smul<"smul", mul>; class T2SMLAL<bits<3> op22_20, bits<4> op7_4, string opc, list<dag> pattern>
defm t2SMLA : T2I_smla<"smla", mul>; : T2FourReg_mac<1, op22_20, op7_4,
(outs rGPR:$Ra, rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm),
IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
// Halfword multiple accumulate long: SMLAL<x><y> // Halfword multiple accumulate long: SMLAL<x><y>
def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd), def t2SMLALBB : T2SMLAL<0b100, 0b1000, "smlalbb", []>;
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm", def t2SMLALBT : T2SMLAL<0b100, 0b1001, "smlalbt", []>;
[/* For disassembly only; pattern left blank */]>, def t2SMLALTB : T2SMLAL<0b100, 0b1010, "smlaltb", []>;
Requires<[IsThumb2, HasDSP]>; def t2SMLALTT : T2SMLAL<0b100, 0b1011, "smlaltt", []>;
def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsThumb2, HasDSP]>;
// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc>
def t2SMUAD: T2ThreeReg_mac< : T2ThreeReg_mac<0, op22_20, op7_4,
0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), (outs rGPR:$Rd),
IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>, (ins rGPR:$Rn, rGPR:$Rm),
Requires<[IsThumb2, HasDSP]> { IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", []>,
let Inst{15-12} = 0b1111;
}
def t2SMUADX:T2ThreeReg_mac<
0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{15-12} = 0b1111;
}
def t2SMUSD: T2ThreeReg_mac<
0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{15-12} = 0b1111;
}
def t2SMUSDX:T2ThreeReg_mac<
0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]> { Requires<[IsThumb2, HasDSP]> {
let Inst{15-12} = 0b1111; let Inst{15-12} = 0b1111;
} }
def t2SMLAD : T2FourReg_mac<
0, 0b010, 0b0000, (outs rGPR:$Rd), // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad", def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad">;
"\t$Rd, $Rn, $Rm, $Ra", []>, def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx">;
Requires<[IsThumb2, HasDSP]>; def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd">;
def t2SMLADX : T2FourReg_mac< def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx">;
0, 0b010, 0b0001, (outs rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx", class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc>
"\t$Rd, $Rn, $Rm, $Ra", []>, : T2FourReg_mac<0, op22_20, op7_4,
Requires<[IsThumb2, HasDSP]>; (outs rGPR:$Rd),
def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd", IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", []>,
"\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
"\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>; Requires<[IsThumb2, HasDSP]>;
def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx", def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad">;
"\t$Ra, $Rd, $Rn, $Rm", []>, def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx">;
def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd">;
def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx">;
class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc>
: T2FourReg_mac<1, op22_20, op7_4,
(outs rGPR:$Ra, rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm),
IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>; Requires<[IsThumb2, HasDSP]>;
def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Division Instructions. // Division Instructions.
// Signed and unsigned division on v7-M // Signed and unsigned division on v7-M
// //
def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
"sdiv", "\t$Rd, $Rn, $Rm", "sdiv", "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
Requires<[HasDivide, IsThumb, HasV8MBaseline]> { Requires<[HasDivide, IsThumb, HasV8MBaseline]> {
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