AMDGPU: Added v_mad instruction.

[wdng]

Summary

Added v_mad_16 instruction definition.

[• tstellarAMD]

The commit subject should be be prefixed with AMDGPU:

lib/Target/AMDGPU/VIInstructions.td

78–83

Can we also add a pattern and a test with this patch?

[wdng]

This pattern has been tested in LIT test mad_uint24.ll, which is a part of fp16 implementation.

[arsenm]

lib/Target/AMDGPU/VIInstructions.td

82

The unsigned version should be also added

281–284

This should be left for the i16 patch

[wdng]

Pattern is added for LIT test mad_uint24.ll

[wdng]

lib/Target/AMDGPU/VIInstructions.td

281–284

Yes, we may not need the pattern. For this patch, we may only need to add the instruction definition for the time being.

[arsenm]

lib/Target/AMDGPU/VIInstructions.td

281–284

The pattern will do nothing here, so yes only the definitions

286

This is also trying to use half mul for integer mul

[wdng]

Added v_mad_u16 instruction definition.

[wdng]

lib/Target/AMDGPU/VIInstructions.td

87

Could you please say in more details? Thanks!

[arsenm]

The v_mad_f16 instruction is also missing

lib/Target/AMDGPU/VIInstructions.td

82–83

These aren't the opcode values I see in the manual

[wdng]

1. Modified opcode for v_mad_u16, v_mad_i16 to make it consistant with the GCN manual.
2. Added v_mad_f16 instruction definition.

[arsenm]

With the capitalization fix LGTM

lib/Target/AMDGPU/VIInstructions.td

82

All of the other opcodes use lower case letters in the hex.

lib/Target/AMDGPU/SIInstrInfo.td

 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i32, untyped]>;
 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
+def VOP_I16_I16_I16_I16 : VOPProfile <[i32, i32, i32, i32, untyped]>;
 
 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
 

lib/Target/AMDGPU/VIInstructions.td

 } // End isCommutable = 1
 defm V_LDEXP_F16 : VOP2Inst <vop2<0,0x33>, "v_ldexp_f16", VOP_F16_F16_I16>;
 
+//===----------------------------------------------------------------------===//
+// VOP3 Instructions
+//===----------------------------------------------------------------------===//
+let isCommutable = 1 in {
+    defm V_MAD_I16 : VOP3Inst <vop3<0, 0x34>, "v_mad_i16", VOP_I16_I16_I16_I16>;
+}
 } // let DisableSIDecoder = 1
 
 // Aliases to simplify matching of floating-point instructions that

     (V_CVT_F16_F32_e32 $src)
 >;
 
+def : Pat<
+    (add (mul i16:$src0, i16:$src1), i16:$src2),
+    (V_MAD_I16 i16:$src0, i16:$src1, i16:$src2)
+>;
+
+defm : Arithmetic_i16_Pats<mul, V_MUL_F16_e32>;
 
 defm : Arithmetic_i16_Pats<add, V_ADD_U16_e32>;
 defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e32>;