[docs] Update AMDGPU relocation information

[kzhuravl]

Summary

• Added new notation for specifying relocation calculation
• Renamed:
  • R_AMDGPU_32_LOW -> R_AMDGPU_ABS32_LO
  • R_AMDGPU_32_HIGH -> R_AMDGPU_ABS32_HI
  • R_AMDGPU_64 -> R_AMDGPU_ABS64
• Added:
  • R_AMDGPU_REL32
  • R_AMDGPU_REL64
  • R_AMDGPU_ABS32
• Updated calculations for relative relocations

[kzhuravl]

Add missing "="

[• rafael]

This drop R_AMDGPU_32. Don't you need it for dwarf?

[kzhuravl]

We are intending to use R_AMDGPU_ABS32_LO for dwarf

[kzhuravl]

Try to eliminate confusion: renamed R_AMDGPU_ABS32_LO to R_AMDGPU_ABS32

[• rafael]

Don't you need an actual R_AMDGPU_ABS32_LO too? If you need a _HI I would assume you need a _LO.

What I would expect is

FOO_ABS32: S + A : this has to be a 32 bit value
FOO_ABS32_LO: (S + A) & 0xffffffff: this writes the low 32 bit values of a 64 bit number.

[• tstellarAMD]

I agree with Rafael here, can we keep R_AMDGPU_ABS32_LO and then just add R_AMDGPU_ABS32 as a separate relocation?

[tony-tye]

The old R_AMDGPU_ABS32_LO and the new R_AMDGPU_ABS32 are in fact the same thing. The & 0xffffffff is implicitly done because the result of the R_AMDGPU_ABS32 is a word32 not a word64. So putting in the & 0xffffffff is redundant. The other ABI documents (such as for the x86) do not put in the & 0xffffffff so it seemed best to follow their conventions. R_AMDGPU_ABS32_HI and R_AMDGPU_ABS32 both return 32 bits as they are both defined as word32. They differ in that R_AMDGPU_ABS32_HI takes the address and shifts it right by 32 bits which effectively means that the top 32 bits of the 64 bit address are returned, not the bottom 32 bits.

[kzhuravl]

Added back R_AMDGPU_ABS32_LO, also added R_AMDGPU_ABS32

[• rafael]

Lgtm

docs/CodeGenerator.rst

 
 * **word32** --- This specifies a 32-bit field occupying 4 bytes with arbitrary
   byte alignment. These values use the same byte order as other word values in
   the AMD GPU architecture
 * **word64** --- This specifies a 64-bit field occupying 8 bytes with arbitrary
   byte alignment. These values use the same byte order as other word values in
   the AMD GPU architecture
 
-Following notations are used for specifying relocation types
+Following notations are used for specifying relocation calculations:
 
 * **A** --- Represents the addend used to compute the value of the relocatable
   field
+* **P** --- Represents the place (section offset or address) of the storage unit
+  being relocated (computed using ``r_offset``)
 * **S** --- Represents the value of the symbol whose index resides in the
   relocation entry
 
 AMDGPU Backend generates *Elf64_Rela* relocation records with the following
 supported relocation types:
 
-  ====================  =====  ==========  ============================
-  Relocation type       Value  Field       Calculation
-  ====================  =====  ==========  ============================
-  ``R_AMDGPU_NONE``     0      ``none``    ``none``
-  ``R_AMDGPU_32_LOW``   1      ``word32``  (S + A) & 0xFFFFFFFF
-  ``R_AMDGPU_32_HIGH``  2      ``word32``  ((S + A) >> 32) & 0xFFFFFFFF
-  ``R_AMDGPU_64``       3      ``word64``  S + A
-  ``R_AMDGPU_32``       4      ``word32``  S + A
-  ====================  =====  ==========  ============================
-
-Only R_AMDGPU_32_LOW and R_AMDGPU_32_HIGH can be handled by the
-dynamic linker.  The rest must be statically resolved.
+  =====================  =====  ==========  =============
+  Relocation type        Value  Field       Calculation
+  =====================  =====  ==========  =============
+  ``R_AMDGPU_NONE``      0      ``none``    ``none``
+  ``R_AMDGPU_ABS32_LO``  1      ``word32``  S + A
+  ``R_AMDGPU_ABS32_HI``  2      ``word32``  (S + A) >> 32
+  ``R_AMDGPU_ABS64``     3      ``word64``  S + A
+  ``R_AMDGPU_REL32``     4      ``word32``  S + A - P
+  ``R_AMDGPU_REL64``     5      ``word64``  S + A - P
+  =====================  =====  ==========  =============