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[AVX512] Fix load opcode for fast isel.
ClosedPublic

Authored by igorb on Jun 7 2016, 5:07 AM.

Reviewers

delena
craig.topper

Commits

Summary

[AVX512] Fix load opcode for fast isel.

igorb retitled this revision from to [AVX512] Fix load opcode for fast isel..

igorb updated this object.

igorb set the repository for this revision to rL LLVM.

igorb added a subscriber: llvm-commits.

any test?

Test case added.

delena edited edge metadata.

This revision is now accepted and ready to land.Jun 7 2016, 5:34 AM

This revision was automatically updated to reflect the committed changes.

Path

Size

lib/

Target/

X86/

2 lines

Show First 20 Lines • Show All 446 Lines • ▼ Show 20 Lines	case MVT::v8f64:
break;		break;
case MVT::v8i64:		case MVT::v8i64:
case MVT::v16i32:		case MVT::v16i32:
case MVT::v32i16:		case MVT::v32i16:
case MVT::v64i8:		case MVT::v64i8:
assert(Subtarget->hasAVX512());		assert(Subtarget->hasAVX512());
// Note: There are a lot more choices based on type with AVX-512, but		// Note: There are a lot more choices based on type with AVX-512, but
// there's really no advantage when the load isn't masked.		// there's really no advantage when the load isn't masked.
Opc = (Alignment >= 64) ? X86::VMOVDQA64Zmr : X86::VMOVDQU64Zmr;		Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm;
RC = &X86::VR512RegClass;		RC = &X86::VR512RegClass;
break;		break;
}		}

ResultReg = createResultReg(RC);		ResultReg = createResultReg(RC);
MachineInstrBuilder MIB =		MachineInstrBuilder MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);		BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
addFullAddress(MIB, AM);		addFullAddress(MIB, AM);
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