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Implement aarch64 neon instructio​n class SIMD Perm - Clang
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Authored by Jiangning on Oct 31 2013, 1:39 AM.

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t.p.northover

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Hi Jiangning,

I've got one question (well, stated as a comment) about this Clang stuff.

Cheers.

Tim.

lib/CodeGen/CGBuiltin.cpp
2374–2375

If I'm reading correctly these cases (the legacy ARM zip/uzp/trn intrinsics) are neither tested in this patch nor implemented on the LLVM side.

Hi Tim,

Are you talking about the intrinsics without digit suffix like vuzp_s8?
They looks like legacy for me. If yes, I think this is already covered. I
have test like the followings,

int8x8x2_t test_vuzp_s8(int8x8_t a, int8x8_t b) {

// CHECK: test_vuzp_s8
return vuzp_s8(a, b);
// CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
// CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b

}

Thanks,
-Jiangning

2013/11/6 Tim Northover <t.p.northover@gmail.com>

Hi Jiangning,

I've got one question (well, stated as a comment) about this Clang stuff.

Cheers.

Tim.

Comment at: lib/CodeGen/CGBuiltin.cpp:2374-2375
@@ -2373,1 +2373,4 @@

// in aarch64-neon-intrinsics.c so far.

+ case AArch64::BIbuiltin_neon_vuzp_v:
+ return EmitARMBuiltinExpr(ARM::BI
builtin_neon_vuzp_v, E);

+ case AArch64::BI__builtin_neon_vuzpq_v:

If I'm reading correctly these cases (the legacy ARM zip/uzp/trn
intrinsics) are neither tested in this patch nor implemented on the LLVM
side.

http://llvm-reviews.chandlerc.com/D2075

t.p.northover accepted this revision.Apr 3 2014, 4:50 AM
Eugene.Zelenko closed this revision.Oct 3 2016, 7:07 PM
Eugene.Zelenko added a subscriber: Eugene.Zelenko.

Committed in rL194124.