[NVPTX] Added NVVMIntrRange pass

[tra]

Summary

NVVMIntrRange adds !range metadata to calls of NVVM intrinsics
that return values within known limited range.

This allows LLVM to generate better code for indexing arrays
based on tid/ctaid which is a frequently used pattern in CUDA code.

[tra]

Updated file name & description in the copyright banner.

[jlebar]

\o/

lib/Target/NVPTX/NVPTXTargetMachine.cpp

181

I have no idea if this is the right way to pass this information to the pass. Seems reasonable to me, though.

lib/Target/NVPTX/NVVMIntrRange.cpp

11

calls to

12

a limited range

37

I think at least a comment, and possibly more descriptive names (blockMaxes / gridMaxes?) would be helpful to readers.

Actually, since you don't use the fact that these are structs at all, maybe just six member variables would be clearer. maxBlockX, maxThreadZ, etc. What do you think?

61

Maybe indicate that the range is [Low, High)?

67

We're already using namespace llvm, so don't need "llvm::" here.

test/CodeGen/NVPTX/intrinsic-old.ll

10–11

Probably shouldn't do it in this patch, but FYI if you add CHECK-LABEL: @foo in front of each function, that will make it a lot easier to debug if it fails. CHECK-LABEL essentially partitions the checks.

Although I think it applies only to CHECKs, not e.g. RANGEs.

314

It looks like we're covering everything other than warpSize -- can we add that one too, for completeness?

[jingyue]

Have you considered letting Clang (instead of a late-stage IR pass) add these ranges? These ranges are useful for some target-independent IR passes, e.g. those using ValueTracking (D4150).

lib/Target/NVPTX/NVVMIntrRange.cpp

36

Maybe name them BlockDim and GridDim

61

Can you comment on whether the range is [Low, High) or [Low, High]?

[tra]

In D20644#440055, @jingyue wrote:

Have you considered letting Clang (instead of a late-stage IR pass) add these ranges? These ranges are useful for some target-independent IR passes, e.g. those using ValueTracking (D4150).

This pass runs at the very beginning of optimization pipeline. Justin created hook for early target-specific passes in D18616.

lib/Target/NVPTX/NVVMIntrRange.cpp

37

I've made names more descriptive. IMO struct fits quite well for describing dimensions/indexes of 3d grid.

test/CodeGen/NVPTX/intrinsic-old.ll

10–11

Having -LABEL does not matter much in this case as each function checks for its own unique register and that applies to both CHECK and RANGE.

314

ptx.read.* and nvvm.read.ptx.sreg.* appear to have diverged.
There's no llvm.ptx.read.warpsize, so it's not in this file.
We apparently don't test nvvm.read.ptx.sreg.* intrinsics much, either.

I can add a range test for nvvm.read.ptx.sreg.warpsize to this patch, but it looks like there's enough work for a separate patch.

[tra]

Addressed Justin's comments.

[jingyue]

test/CodeGen/NVPTX/intrinsic-old.ll

315

Trailing blank line

[jlebar]

it looks like there's enough work for a separate patch.

I'm happy if you want to do it in a separate patch, but we should definitely add testing of important intrinsics like these, one way or another.

LGTM aside from the apparent integer overflow.

lib/Target/NVPTX/NVVMIntrRange.cpp

62

MaxGridSize.x is INT_MAX for sm_30+. Then we add 1 to it, and store in a signed int...

[tra]

Use uint64_t to pass range limits so we don't risk overflow on the way to ConstantInt::get().

[tra]

lib/Target/NVPTX/NVVMIntrRange.cpp

62

Changed arg type to uint64_t.
As for the range itself, it apparently allows wrapping, so exclusive high boundary wrapped to negative value should be OK. In any case we don't have any other way to encode it considering that range values must be the same as return type which is i32 in this case.

lib/Target/NVPTX/CMakeLists.txt

set(NVPTXCodeGen_sources
   NVPTXMCExpr.cpp
   NVPTXPrologEpilogPass.cpp
   NVPTXRegisterInfo.cpp
   NVPTXReplaceImageHandles.cpp
   NVPTXSubtarget.cpp
   NVPTXTargetMachine.cpp
   NVPTXTargetTransformInfo.cpp
   NVPTXUtilities.cpp
+  NVVMIntrRange.cpp
   NVVMReflect.cpp
   )
 
 add_llvm_target(NVPTXCodeGen ${NVPTXCodeGen_sources})
 
 add_subdirectory(TargetInfo)
 add_subdirectory(InstPrinter)
 add_subdirectory(MCTargetDesc)

lib/Target/NVPTX/NVPTX.h

 }
 
 FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
                                  llvm::CodeGenOpt::Level OptLevel);
 ModulePass *createNVPTXAssignValidGlobalNamesPass();
 ModulePass *createGenericToNVVMPass();
 FunctionPass *createNVPTXFavorNonGenericAddrSpacesPass();
 FunctionPass *createNVPTXInferAddressSpacesPass();
+FunctionPass *createNVVMIntrRangePass(unsigned int SmVersion);
 FunctionPass *createNVVMReflectPass();
 FunctionPass *createNVVMReflectPass(const StringMap<int> &Mapping);
 MachineFunctionPass *createNVPTXPrologEpilogPass();
 MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
 FunctionPass *createNVPTXImageOptimizerPass();
 FunctionPass *createNVPTXLowerKernelArgsPass(const NVPTXTargetMachine *TM);
 BasicBlockPass *createNVPTXLowerAllocaPass();
 MachineFunctionPass *createNVPTXPeephole();

lib/Target/NVPTX/NVPTXTargetMachine.cpp

 using namespace llvm;
 
 static cl::opt<bool> UseInferAddressSpaces(
     "nvptx-use-infer-addrspace", cl::init(false), cl::Hidden,
     cl::desc("Optimize address spaces using NVPTXInferAddressSpaces instead of "
              "NVPTXFavorNonGenericAddrSpaces"));
 
 namespace llvm {
+void initializeNVVMIntrRangePass(PassRegistry&);
 void initializeNVVMReflectPass(PassRegistry&);
 void initializeGenericToNVVMPass(PassRegistry&);
 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
 void initializeNVPTXInferAddressSpacesPass(PassRegistry &);
 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
 void initializeNVPTXLowerKernelArgsPass(PassRegistry &);
 void initializeNVPTXLowerAllocaPass(PassRegistry &);
 }
 
 extern "C" void LLVMInitializeNVPTXTarget() {
   // Register the target.
   RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
   RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
 
   // FIXME: This pass is really intended to be invoked during IR optimization,
   // but it's very NVPTX-specific.
   PassRegistry &PR = *PassRegistry::getPassRegistry();
   initializeNVVMReflectPass(PR);
+  initializeNVVMIntrRangePass(PR);
   initializeGenericToNVVMPass(PR);
   initializeNVPTXAllocaHoistingPass(PR);
   initializeNVPTXAssignValidGlobalNamesPass(PR);
   initializeNVPTXFavorNonGenericAddrSpacesPass(PR);
   initializeNVPTXInferAddressSpacesPass(PR);
   initializeNVPTXLowerKernelArgsPass(PR);
   initializeNVPTXLowerAllocaPass(PR);
   initializeNVPTXLowerAggrCopiesPass(PR);

 } // end anonymous namespace
 
 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new NVPTXPassConfig(this, PM);
 }
 
 void NVPTXTargetMachine::addEarlyAsPossiblePasses(PassManagerBase &PM) {
   PM.add(createNVVMReflectPass());
+  PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion()));
 }
 
 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
   return TargetIRAnalysis([this](const Function &F) {
     return TargetTransformInfo(NVPTXTTIImpl(this, F));
   });
 }
 

lib/Target/NVPTX/NVVMIntrRange.cpp

+//===- NVVMIntrRange.cpp - Set !range metadata for NVVM intrinsics --------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass adds appropriate !range metadata for calls of NVVM
+// intrinsics that return limited range of values.
+//
+//===----------------------------------------------------------------------===//
+
+#include "NVPTX.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/InstIterator.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "nvvm-intr-range"
+
+namespace llvm { void initializeNVVMIntrRangePass(PassRegistry &); }
+
+// Add !range metadata based on limits of given SM variant.
+static cl::opt<unsigned> NVVMIntrRangeSM("nvvm-intr-range-sm", cl::init(20),
+                                         cl::Hidden, cl::desc("SM variant"));
+
+namespace {
+class NVVMIntrRange : public FunctionPass {
+ private:
+   struct {
+     unsigned x, y, z;
+   } block, grid;
+
+ public:
+   static char ID;
+   NVVMIntrRange() : NVVMIntrRange(NVVMIntrRangeSM) {}
+   NVVMIntrRange(unsigned int SmVersion)
+       : FunctionPass(ID), block{1024, 1024, 64},
+         grid{SmVersion >= 30 ? 0x7fffffffu : 0xffffu, 0xffff, 0xffff} {
+     initializeNVVMIntrRangePass(*PassRegistry::getPassRegistry());
+   }
+
+   bool runOnFunction(Function &) override;
+};
+}
+
+FunctionPass *llvm::createNVVMIntrRangePass(unsigned int SmVersion) {
+  return new NVVMIntrRange(SmVersion);
+}
+
+char NVVMIntrRange::ID = 0;
+INITIALIZE_PASS(NVVMIntrRange, "nvvm-intr-range",
+                "Add !range metadata to NVVM intrinsics.", false, false)
+
+// Adds the passed-in range information as metadata to the passed-in
+// call instruction.
+static bool addRangeMetadata(int Low, int High, CallInst *C) {
+  llvm::LLVMContext &Context = C->getParent()->getContext();
+  IntegerType *Int32Ty = Type::getInt32Ty(Context);
+  llvm::Metadata *LowAndHigh[] = {
+      ConstantAsMetadata::get(llvm::ConstantInt::get(Int32Ty, Low)),
+      ConstantAsMetadata::get(llvm::ConstantInt::get(Int32Ty, High))};
+  C->setMetadata(llvm::LLVMContext::MD_range,
+                 llvm::MDNode::get(Context, LowAndHigh));
+  return true;
+}
+
+bool NVVMIntrRange::runOnFunction(Function &F) {
+  // Go through the calls in this function.
+  bool Changed = false;
+  for (Instruction &I : instructions(F)) {
+    CallInst *Call = dyn_cast<CallInst>(&I);
+    if (!Call)
+      continue;
+
+    if (Function *Callee = Call->getCalledFunction()) {
+      switch (Callee->getIntrinsicID()) {
+      // Index within block
+      case Intrinsic::ptx_read_tid_x:
+      case Intrinsic::nvvm_read_ptx_sreg_tid_x:
+        Changed |= addRangeMetadata(0, block.x, Call);
+        break;
+      case Intrinsic::ptx_read_tid_y:
+      case Intrinsic::nvvm_read_ptx_sreg_tid_y:
+        Changed |= addRangeMetadata(0, block.y, Call);
+        break;
+      case Intrinsic::ptx_read_tid_z:
+      case Intrinsic::nvvm_read_ptx_sreg_tid_z:
+        Changed |= addRangeMetadata(0, block.z, Call);
+        break;
+
+      // Block size
+      case Intrinsic::ptx_read_ntid_x:
+      case Intrinsic::nvvm_read_ptx_sreg_ntid_x:
+        Changed |= addRangeMetadata(1, block.x+1, Call);
+        break;
+      case Intrinsic::ptx_read_ntid_y:
+      case Intrinsic::nvvm_read_ptx_sreg_ntid_y:
+        Changed |= addRangeMetadata(1, block.y+1, Call);
+        break;
+      case Intrinsic::ptx_read_ntid_z:
+      case Intrinsic::nvvm_read_ptx_sreg_ntid_z:
+        Changed |= addRangeMetadata(1, block.z+1, Call);
+        break;
+
+      // Index within grid
+      case Intrinsic::ptx_read_ctaid_x:
+      case Intrinsic::nvvm_read_ptx_sreg_ctaid_x:
+        Changed |= addRangeMetadata(0, grid.x, Call);
+        break;
+      case Intrinsic::ptx_read_ctaid_y:
+      case Intrinsic::nvvm_read_ptx_sreg_ctaid_y:
+        Changed |= addRangeMetadata(0, grid.y, Call);
+        break;
+      case Intrinsic::ptx_read_ctaid_z:
+      case Intrinsic::nvvm_read_ptx_sreg_ctaid_z:
+        Changed |= addRangeMetadata(0, grid.z, Call);
+        break;
+
+      // Grid size
+      case Intrinsic::ptx_read_nctaid_x:
+      case Intrinsic::nvvm_read_ptx_sreg_nctaid_x:
+        Changed |= addRangeMetadata(1, grid.x+1, Call);
+        break;
+      case Intrinsic::ptx_read_nctaid_y:
+      case Intrinsic::nvvm_read_ptx_sreg_nctaid_y:
+        Changed |= addRangeMetadata(1, grid.y+1, Call);
+        break;
+      case Intrinsic::ptx_read_nctaid_z:
+      case Intrinsic::nvvm_read_ptx_sreg_nctaid_z:
+        Changed |= addRangeMetadata(1, grid.z+1, Call);
+        break;
+
+      // warp size is constant 32.
+      case Intrinsic::nvvm_read_ptx_sreg_warpsize:
+        Changed |= addRangeMetadata(32, 32+1, Call);
+        break;
+
+      // Lane ID is [0..warpsize)
+      case Intrinsic::ptx_read_laneid:
+        Changed |= addRangeMetadata(0, 32, Call);
+        break;
+
+      default:
+        break;
+      }
+    }
+  }
+
+  return Changed;
+}

test/CodeGen/NVPTX/intrinsic-old.ll

 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
+; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -nvvm-intr-range \
+; RUN:   | FileCheck --check-prefix=RANGE --check-prefix=RANGE_20 %s
+; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda \
+; RUN:    -nvvm-intr-range -nvvm-intr-range-sm=30 \
+; RUN:   | FileCheck --check-prefix=RANGE --check-prefix=RANGE_30 %s
 
 define ptx_device i32 @test_tid_x() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %tid.x;
+; RANGE: call i32 @llvm.ptx.read.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.tid.x()
   ret i32 %x
 }
 
 define ptx_device i32 @test_tid_y() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %tid.y;
+; RANGE: call i32 @llvm.ptx.read.tid.y(), !range ![[BLK_IDX_XY]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.tid.y()
   ret i32 %x
 }
 
 define ptx_device i32 @test_tid_z() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %tid.z;
+; RANGE: call i32 @llvm.ptx.read.tid.z(), !range ![[BLK_IDX_Z:[0-9]+]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.tid.z()
   ret i32 %x
 }
 
 define ptx_device i32 @test_tid_w() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %tid.w;
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.tid.w()
   ret i32 %x
 }
 
 define ptx_device i32 @test_ntid_x() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.x;
+; RANGE: call i32 @llvm.ptx.read.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.ntid.x()
   ret i32 %x
 }
 
 define ptx_device i32 @test_ntid_y() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.y;
+; RANGE: call i32 @llvm.ptx.read.ntid.y(), !range ![[BLK_SIZE_XY]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.ntid.y()
   ret i32 %x
 }
 
 define ptx_device i32 @test_ntid_z() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.z;
+; RANGE: call i32 @llvm.ptx.read.ntid.z(), !range ![[BLK_SIZE_Z:[0-9]+]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.ntid.z()
   ret i32 %x
 }
 
 define ptx_device i32 @test_ntid_w() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.w;
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.ntid.w()
   ret i32 %x
 }
 
 define ptx_device i32 @test_laneid() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %laneid;
+; RANGE: call i32 @llvm.ptx.read.laneid(), !range ![[LANEID:[0-9]+]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.laneid()
   ret i32 %x
 }
 
 define ptx_device i32 @test_warpid() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %warpid;
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.warpid()
   ret i32 %x
 }
 
 define ptx_device i32 @test_nwarpid() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %nwarpid;
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.nwarpid()
   ret i32 %x
 }
 
-define ptx_device i32 @test_ctaid_x() {
-; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.x;
-; CHECK: ret;
-  %x = call i32 @llvm.ptx.read.ctaid.x()
-  ret i32 %x
-}
-
 define ptx_device i32 @test_ctaid_y() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.y;
+; RANGE: call i32 @llvm.ptx.read.ctaid.y(), !range ![[GRID_IDX_YZ:[0-9]+]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.ctaid.y()
   ret i32 %x
 }
 
 define ptx_device i32 @test_ctaid_z() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.z;
+; RANGE: call i32 @llvm.ptx.read.ctaid.z(), !range ![[GRID_IDX_YZ]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.ctaid.z()
   ret i32 %x
 }
 
-define ptx_device i32 @test_ctaid_w() {
-; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.w;
+define ptx_device i32 @test_ctaid_x() {
+; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.x;
+; RANGE_30: call i32 @llvm.ptx.read.ctaid.x(), !range ![[GRID_IDX_X:[0-9]+]]
+; RANGE_20: call i32 @llvm.ptx.read.ctaid.x(), !range ![[GRID_IDX_YZ]]
 ; CHECK: ret;
-  %x = call i32 @llvm.ptx.read.ctaid.w()
+  %x = call i32 @llvm.ptx.read.ctaid.x()
   ret i32 %x
 }
 
-define ptx_device i32 @test_nctaid_x() {
-; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.x;
+define ptx_device i32 @test_ctaid_w() {
+; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.w;
 ; CHECK: ret;
-  %x = call i32 @llvm.ptx.read.nctaid.x()
+  %x = call i32 @llvm.ptx.read.ctaid.w()
   ret i32 %x
 }
 
 define ptx_device i32 @test_nctaid_y() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.y;
+; RANGE: call i32 @llvm.ptx.read.nctaid.y(), !range ![[GRID_SIZE_YZ:[0-9]+]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.nctaid.y()
   ret i32 %x
 }
 
 define ptx_device i32 @test_nctaid_z() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.z;
+; RANGE: call i32 @llvm.ptx.read.nctaid.z(), !range ![[GRID_SIZE_YZ]]
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.nctaid.z()
   ret i32 %x
 }
 
+define ptx_device i32 @test_nctaid_x() {
+; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.x;
+; RANGE_30: call i32 @llvm.ptx.read.nctaid.x(), !range ![[GRID_SIZE_X:[0-9]+]]
+; RANGE_20: call i32 @llvm.ptx.read.nctaid.x(), !range ![[GRID_SIZE_YZ]]
+; CHECK: ret;
+  %x = call i32 @llvm.ptx.read.nctaid.x()
+  ret i32 %x
+}
+
+
 define ptx_device i32 @test_nctaid_w() {
 ; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.w;
 ; CHECK: ret;
   %x = call i32 @llvm.ptx.read.nctaid.w()
   ret i32 %x
 }
 
 define ptx_device i32 @test_smid() {

 declare i64 @llvm.ptx.read.clock64()
 
 declare i32 @llvm.ptx.read.pm0()
 declare i32 @llvm.ptx.read.pm1()
 declare i32 @llvm.ptx.read.pm2()
 declare i32 @llvm.ptx.read.pm3()
 
 declare void @llvm.ptx.bar.sync(i32 %i)
+
+; RANGE-DAG: ![[BLK_IDX_XY]] = !{i32 0, i32 1024}
+; RANGE-DAG: ![[BLK_IDX_Z]] = !{i32 0, i32 64}
+; RANGE-DAG: ![[BLK_SIZE_XY]] = !{i32 1, i32 1025}
+; RANGE-DAG: ![[BLK_SIZE_Z]] = !{i32 1, i32 65}
+; RANGE-DAG: ![[LANEID]] = !{i32 0, i32 32}
+; RANGE_30-DAG: ![[GRID_IDX_X]] = !{i32 0, i32 2147483647}
+; RANGE-DAG: ![[GRID_IDX_YZ]] = !{i32 0, i32 65535}
+; RANGE_30-DAG: ![[GRID_SIZE_X]] = !{i32 1, i32 -2147483648}
+; RANGE-DAG: ![[GRID_SIZE_YZ]] = !{i32 1, i32 65536}
+