[Sparc][LEON] Add LEON-specific CASA instruction.

[lero_chris]

Summary

Adds the CASA instruction for LEON processors.

[lero_chris]

Combined the two ATOMIC_CMP_SWAP legalisation commands into one.

[jyknight]

lib/Target/Sparc/LeonFeatures.td

28

Comment unnecessary.

34

"Support" in the name is weird. How about calling it leoncas.

35

HasLeonCAS

lib/Target/Sparc/Sparc.td

119

Not sure what you mean by 'provides full coverage of'

lib/Target/Sparc/SparcISelLowering.cpp

1620

Should check just one subtarget feature, hasLeonCAS.

But I'd rather not commit these 2 lines that actually turn on support quite yet, as it'll break code using 8 and 16-bit atomics. (Which, of course, are already broken on 64bit sparc, but that's been true all along, and won't be a regression).

I have a patch in progress to support this generically in AtomicExpandPass, but it's not quite ready yet.

1623–1627

Can actually delete these lines I believe. Legal is the default, and Expand isn't useful here, because it's handled via setMaxAtomicSizeInBitsSupported now.

lib/Target/Sparc/SparcInstrInfo.td

52

HasLeonCAS

[lero_chris]

lib/Target/Sparc/Sparc.td

119

OK. The code I took this from in my version has several other LEON features, but I admit that "coverage" is perhaps an unusual choice of words, so I'll alter that. Eventually, there will be more features here - hence "full coverage"

[lero_chris]

Adjustments in line with comments made.

[lero_chris]

Typos fixed in updated code.

[lero_chris]

Query ability to get this code checked-into the trunk by commenting-out lines that will regress atomics behaviour (temporarily)

lib/Target/Sparc/SparcISelLowering.cpp

1620

Can I comment-out these two lines, to be added when the AtomicExpandPass is completed? Leaving them like this will make it difficult to check-in other changes that are upcoming, due to changes in the other files in this review (unrelated to atomics work)

[lero_chris]

To avoid regressions in areas of code being worked on by James Knight, I've removed the section of code that will enable atomics for LEON processors.

When the work on AtomicExpandPass has completed, this section will be re-inserted.

[lero_chris]

Tests are working. CASA instruction is available as inline ASM and a small change will allow full atomics behaviour for LEON processors when the AtomicExpandPass is completed.

lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
     return ResTy;
 
   if (getLexer().is(AsmToken::LBrac)) {
     // Memory operand
     Operands.push_back(SparcOperand::CreateToken("[",
                                                  Parser.getTok().getLoc()));
     Parser.Lex(); // Eat the [
 
-    if (Mnemonic == "cas" || Mnemonic == "casx") {
+    if (Mnemonic == "cas" || Mnemonic == "casx" || Mnemonic == "casa") {
       SMLoc S = Parser.getTok().getLoc();
       if (getLexer().getKind() != AsmToken::Percent)
         return MatchOperand_NoMatch;
       Parser.Lex(); // eat %
 
       unsigned RegNo, RegKind;
       if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
         return MatchOperand_NoMatch;

lib/Target/Sparc/LeonFeatures.td

 
 //support to casa instruction; for leon3 subtarget only
 def UMACSMACSupport : SubtargetFeature<
   "hasumacsmac", 
   "HasUmacSmac", 
   "true", 
   "Enable UMAC and SMAC for LEON3 and LEON4 processors"
 >;
+
+
+//===----------------------------------------------------------------------===//
+// CASA Support differs between LEON3-FT GR712RC and LEON3-FT UT699
+// We need to have the option to switch this on and off.
+//===----------------------------------------------------------------------===//
+
+//support to casa instruction; for leon3 subtarget only
+def CASASupport : SubtargetFeature<
+  "casasupport", 
+  "CasaEnabled", 
+  "true", 
+  "Enable CASA instruction for relevant LEON3 and LEON4 processors"
+>;
   
 No newline at end of file

lib/Target/Sparc/Sparc.td

 def : Processor<"at697f", LEON2Itineraries,
                 [FeatureLeon]>;
 
 
 // LEON 3 FT generic
 def : Processor<"leon3", LEON3Itineraries,
                 [FeatureLeon, UMACSMACSupport]>;
 
-// LEON 3 FT (UT699)
-// TO DO: Place-holder: Processor specific features will be added *very* soon here.
+// LEON 3 FT (UT699). Provides full coverage of UT699 - covers all the erratum fixes for LEON3. No support for CASA
 def : Processor<"ut699", LEON3Itineraries, 
                 [FeatureLeon, UMACSMACSupport]>;
 
-// LEON3 FT (GR712RC) 
-// TO DO: Place-holder: Processor specific features will be added *very* soon here.
+// LEON3 FT (GR712RC). Provides full coverage of GR712RC. Supports for CASA 
 def : Processor<"gr712rc", LEON3Itineraries,
-                [FeatureLeon, UMACSMACSupport]>;
+                [FeatureLeon, UMACSMACSupport, CASASupport]>;
 
 // LEON 4 FT generic
 def : Processor<"leon4", LEON4Itineraries,
-                [FeatureLeon, UMACSMACSupport]>;
+                [FeatureLeon, UMACSMACSupport, CASASupport]>;
 
 // LEON 4 FT (GR740) 
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"gr740", LEON4Itineraries, 
-                [FeatureLeon, UMACSMACSupport]>;
+                [FeatureLeon, UMACSMACSupport, CASASupport]>;
 
 //===----------------------------------------------------------------------===//
 // Declare the target which we are implementing
 //===----------------------------------------------------------------------===//
 
 def SparcAsmWriter : AsmWriter {
   string AsmWriterClassName  = "InstPrinter";
   int PassSubtarget = 1;

lib/Target/Sparc/SparcISelLowering.cpp

SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   }
 
   // ATOMICs.
   // Atomics are only supported on Sparcv9. (32bit atomics are also
   // supported by the Leon sparcv8 variant, but we don't support that
   // yet.)
   if (Subtarget->isV9())
     setMaxAtomicSizeInBitsSupported(64);
   else
     setMaxAtomicSizeInBitsSupported(0);
 
   setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
   setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,
                      (Subtarget->isV9() ? Legal: Expand));
 
 
   setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
 
   // Custom Lower Atomic LOAD/STORE
   setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
   setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
 
   if (Subtarget->is64Bit()) {
     setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
if (Subtarget->is64Bit()) {
       setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
       setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
       setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
       setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
       setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
     }
   }
 
+  if (Subtarget->isLeon()) {
+    setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,
+                       Subtarget->casaEnabled() ? Legal: Expand);
+  }
+
+
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
 
   setMinFunctionAlignment(2);
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 }
 
 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {

lib/Target/Sparc/SparcInstrInfo.td

def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
              AssemblerPredicate<"FeatureVIS2">;
 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
              AssemblerPredicate<"FeatureVIS3">;
 
 // HasHardQuad - This is true when the target processor supports quad floating
 // point instructions.
 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
 
+// CASASupported - This is true when the target processor supports the CASA
+// instruction
+def CASASupported : Predicate<"Subtarget->casaEnabled()">;
+
 // HasUMAC_SMAC - This is true when the target processor supports the
 // UMAC and SMAC instructions
 def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
 
 // UseDeprecatedInsts - This predicate is true when the target processor is a
 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
 // to use when appropriate.  In either of these cases, the instruction selector
 // will pick deprecated instructions.
def POPCrr : F3_1<2, 0b101110,
                     "popc $rs2, $rd", []>, Requires<[HasV9]>;
 def : Pat<(ctpop i32:$src),
           (POPCrr (SRLri $src, 0))>;
 
 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
  def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
                     "membar $simm13", []>;
 
-// TODO: Should add a CASArr variant. In fact, the CAS instruction,
-// unlike other instructions, only comes in a form which requires an
-// ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the
-// default unprivileged ASI for SparcV9.  (Also of note: some modern
-// SparcV8 implementations provide CASA as an extension, but require
-// the use of SparcV8's default ASI, 0xA ("User Data") instead.)
+// The CAS instruction, unlike other instructions, only comes in a 
+// form which requires an ASI be provided. The ASI value hardcoded 
+// here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.
 let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
   def CASrr: F3_1_asi<3, 0b111100,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                      IntRegs:$swap),
                  "cas [$rs1], $rs2, $rd",
                  [(set i32:$rd,
                      (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
 
+
+// CASA supported on some LEON3 and all LEON4 processors.
+// This version can be automatically lowered from C code, selecting ASI 10
+let Predicates = [CASASupported], Constraints = "$swap = $rd", asi = 0b00001010 in
+  def CASAasi10: F3_1_asi<3, 0b111100,
+                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
+                                     IntRegs:$swap),
+                 "casa [$rs1] 10, $rs2, $rd",
+                 [(set i32:$rd,
+                     (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
+                 
+// CASA supported on some LEON3 and all LEON4 processors. Same pattern as
+// CASrr, above, but with a different ASI. This version is supported for
+// inline assembly lowering only. 
+let Predicates = [CASASupported], Constraints = "$swap = $rd" in
+  def CASArr: F3_1_asi<3, 0b111100,
+                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
+                                     IntRegs:$swap, i8imm:$asi),
+                 "casa [$rs1] $asi, $rs2, $rd", []>;
+                
 // TODO: Add DAG sequence to lower these instructions. Currently, only provided
 // as inline assembler-supported instructions. 
 let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in {
   def SMACrr :  F3_1<2, 0b111111,
                    (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
                    "smac $rs1, $rs2, $rd",
                    [], IIC_smac_umac>;
 

lib/Target/Sparc/SparcSubtarget.h

 namespace llvm {
 class StringRef;
 
 class SparcSubtarget : public SparcGenSubtargetInfo {
   Triple TargetTriple;
   virtual void anchor();
   bool IsV9;
   bool IsLeon;
-  bool HasUmacSmac;
   bool V8DeprecatedInsts;
   bool IsVIS, IsVIS2, IsVIS3;
   bool Is64Bit;
   bool HasHardQuad;
   bool UsePopc;
+
+  // LEON features
+  bool HasUmacSmac;
+  bool CasaEnabled;
+
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   SparcFrameLowering FrameLowering;
 
 public:
   SparcSubtarget(const Triple &TT, const std::string &CPU,
                  const std::string &FS, const TargetMachine &TM, bool is64bit);
public:
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
   bool enableMachineScheduler() const override;
 
   bool isV9() const { return IsV9; }
   bool isLeon() const { return IsLeon; }
-  bool hasUmacSmac() const { return HasUmacSmac; }
   bool isVIS() const { return IsVIS; }
   bool isVIS2() const { return IsVIS2; }
   bool isVIS3() const { return IsVIS3; }
   bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
   bool hasHardQuad() const { return HasHardQuad; }
   bool usePopc() const { return UsePopc; }
 
+  // Leon options
+  bool hasUmacSmac() const { return HasUmacSmac; }
+  bool casaEnabled() const { return CasaEnabled; }
+
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
   SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
   bool is64Bit() const { return Is64Bit; }
 
   /// The 64-bit ABI uses biased stack and frame pointers, so the stack frame

lib/Target/Sparc/SparcSubtarget.cpp

 SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                                 StringRef FS) {
   IsV9 = false;
   IsLeon = false;
   V8DeprecatedInsts = false;
   IsVIS = false;
   HasHardQuad = false;
   UsePopc = false;
+
+  // Leon features
+  CasaEnabled = false;
   HasUmacSmac = false;
 
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = (Is64Bit) ? "v9" : "v8";
 
   // Parse features string.

test/MC/Sparc/leon-instructions.s

-! RUN: llvm-mc %s -arch=sparc -mcpu=leon3 -show-encoding | FileCheck %s
-! RUN: llvm-mc %s -arch=sparc -mcpu=ut699 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -arch=sparc -mcpu=leon3 -show-encoding | FileCheck %s -check-prefix=CHECK_NO_CASA
+! RUN: llvm-mc %s -arch=sparc -mcpu=ut699 -show-encoding | FileCheck %s -check-prefix=CHECK_NO_CASA
 ! RUN: llvm-mc %s -arch=sparc -mcpu=gr712rc -show-encoding | FileCheck %s
 ! RUN: llvm-mc %s -arch=sparc -mcpu=leon4 -show-encoding | FileCheck %s
 ! RUN: llvm-mc %s -arch=sparc -mcpu=gr740 -show-encoding | FileCheck %s
 
 
+        ! CHECK: casa [%i0] 10, %l6, %o2    ! encoding: [0xd5,0xe6,0x01,0x56]
+        casa [%i0] 10, %l6, %o2
+
+        ! CHECK: casa [%i0] 5, %l6, %o2    ! encoding: [0xd5,0xe6,0x00,0xb6]
+        casa [%i0] 5, %l6, %o2
+
         ! CHECK: umac %i0, %l6, %o2    ! encoding: [0x95,0xf6,0x00,0x16]
+        ! CHECK_NO_CASA: umac %i0, %l6, %o2    ! encoding: [0x95,0xf6,0x00,0x16]
         umac %i0, %l6, %o2
 
         ! CHECK: smac %i0, %l6, %o2    ! encoding: [0x95,0xfe,0x00,0x16]
+        ! CHECK_NO_CASA: smac %i0, %l6, %o2    ! encoding: [0x95,0xfe,0x00,0x16]
         smac %i0, %l6, %o2