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Differential D19862

[mips][fastisel] Conditional moves do not have implicit operands.
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Authored by dsanders on May 3 2016, 5:07 AM.

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sdardis
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rGa6cda12179b8: [mips][fastisel] Conditional moves do not have implicit operands.
rL268730: [mips][fastisel] Conditional moves do not have implicit operands.

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dsanders updated this revision to Diff 55973.May 3 2016, 5:07 AM
dsanders retitled this revision from to [mips][fastisel] Conditional moves do not have implicit operands..
dsanders updated this object.
dsanders added a reviewer: sdardis.
dsanders added a subscriber: llvm-commits.
Herald added subscribers: sdardis, dsanders. · View Herald TranscriptMay 3 2016, 5:07 AM
sdardis accepted this revision.May 4 2016, 2:31 AM
sdardis edited edge metadata.

LGTM.

This revision is now accepted and ready to land.May 4 2016, 2:31 AM
dsanders closed this revision.May 6 2016, 6:03 AM
Closed by commit rL268730: [mips][fastisel] Conditional moves do not have implicit operands. (authored by dsanders). · Explain WhyMay 6 2016, 6:03 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
9 lines
test/
CodeGen/
Mips/
Fast-ISel/
4 lines

Diff 55973

lib/Target/Mips/MipsFastISel.cpp

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llvm_unreachable("Only switching of a subset of CCs."); llvm_unreachable("Only switching of a subset of CCs.");
} }
unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass); unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
Mips::FCC0, RegState::ImplicitDefine); Mips::FCC0, RegState::ImplicitDefine);
MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg) emitInst(CondMovOpc, ResultReg)
.addReg(RegWithOne) .addReg(RegWithOne)
.addReg(Mips::FCC0) .addReg(Mips::FCC0)
.addReg(RegWithZero, RegState::Implicit); .addReg(RegWithZero);
MI->tieOperands(0, 3);
break; break;
} }
} }
return true; return true;
} }
bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
unsigned Alignment) { unsigned Alignment) {
// //
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test/CodeGen/Mips/Fast-ISel/fpcmpa.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
@f1 = common global float 0.000000e+00, align 4 @f1 = common global float 0.000000e+00, align 4
@f2 = common global float 0.000000e+00, align 4 @f2 = common global float 0.000000e+00, align 4
@b1 = common global i32 0, align 4 @b1 = common global i32 0, align 4
@d1 = common global double 0.000000e+00, align 8 @d1 = common global double 0.000000e+00, align 8
@d2 = common global double 0.000000e+00, align 8 @d2 = common global double 0.000000e+00, align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
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