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Differential D19786

AMDGPU: Make CONST_DATA_PTR available to R600
ClosedPublic

Authored by jvesely on May 1 2016, 9:45 PM.

Details

Reviewers
• tstellarAMD
Commits
rGfbcb754e6661: AMDGPU: Make CONST_DATA_PTR available to R600
rL269474: AMDGPU: Make CONST_DATA_PTR available to R600
Summary

Rename to AMDGPUconstdata_ptr

Diff Detail

Event Timeline

jvesely updated this revision to Diff 55773.May 1 2016, 9:45 PM
jvesely retitled this revision from to AMDGPU: Make CONST_DATA_PTR available to R600.
jvesely updated this object.
jvesely set the repository for this revision to rL LLVM.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptMay 1 2016, 9:45 PM
Herald added a subscriber: arsenm. · View Herald Transcript
jvesely added a child revision: D19792: AMDGPU/R600: Implement loads from constant AS.May 1 2016, 9:58 PM
• tstellarAMD accepted this revision.May 6 2016, 5:09 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.May 6 2016, 5:09 PM
Closed by commit rL269474: AMDGPU: Make CONST_DATA_PTR available to R600 (authored by jvesely). · Explain WhyMay 13 2016, 1:45 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
5 lines
5 lines
2 lines

Diff 55773

lib/Target/AMDGPU/AMDGPUInstrInfo.td

Show All 38 Lines
def AMDGPUFmasOp : SDTypeProfile<1, 4, def AMDGPUFmasOp : SDTypeProfile<1, 4,
[SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>] [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
>; >;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AMDGPU DAG Nodes // AMDGPU DAG Nodes
// //
def AMDGPUconstdata_ptr : SDNode<
"AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
SDTCisVT<0, iPTR>]>
>;
// This argument to this node is a dword address. // This argument to this node is a dword address.
def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>; def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>; def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>; def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
// out = a - floor(a) // out = a - floor(a)
def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>; def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
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lib/Target/AMDGPU/SIInstrInfo.td

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Lines SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v8i32>,
SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]> SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
>; >;
def SIsample : SDSample<"AMDGPUISD::SAMPLE">; def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">; def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
def SIsampled : SDSample<"AMDGPUISD::SAMPLED">; def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">; def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
def SIconstdata_ptr : SDNode<
"AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, i64>,
SDTCisVT<0, i64>]>
>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PatFrags for FLAT instructions // PatFrags for FLAT instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class flat_ld <SDPatternOperator ld> : PatFrag<(ops node:$ptr), class flat_ld <SDPatternOperator ld> : PatFrag<(ops node:$ptr),
(ld node:$ptr), [{ (ld node:$ptr), [{
return isFlatLoad(dyn_cast<MemSDNode>(N)) || return isFlatLoad(dyn_cast<MemSDNode>(N)) ||
isGlobalLoad(dyn_cast<MemSDNode>(N)) || isGlobalLoad(dyn_cast<MemSDNode>(N)) ||
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lib/Target/AMDGPU/SIInstructions.td

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defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>; defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>; defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
let Defs = [SCC] in { let Defs = [SCC] in {
def SI_CONSTDATA_PTR : InstSI < def SI_CONSTDATA_PTR : InstSI <
(outs SReg_64:$dst), (outs SReg_64:$dst),
(ins const_ga:$ptr), (ins const_ga:$ptr),
"", [(set SReg_64:$dst, (i64 (SIconstdata_ptr (tglobaladdr:$ptr))))] "", [(set SReg_64:$dst, (i64 (AMDGPUconstdata_ptr (tglobaladdr:$ptr))))]
> { > {
let SALU = 1; let SALU = 1;
} }
} // End Defs = [SCC] } // End Defs = [SCC]
} // End isCodeGenOnly, isPseudo } // End isCodeGenOnly, isPseudo
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