AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch

[• tstellarAMD]

Summary

We were using v_readlane_b32 with the lane set to zero, but this won't
work if thread 0 is not active.

[arsenm]

LGTM

lib/Target/AMDGPU/SIRegisterInfo.cpp

case AMDGPU::SI_SPILL_S32_RESTORE: {
 
           BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg)
                   .addFrameIndex(Index)                   // frame_idx
                   .addReg(MFI->getScratchRSrcReg())       // scratch_rsrc
                   .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
                   .addImm(i * 4)                          // offset
                   .addMemOperand(MMO);
           BuildMI(*MBB, MI, DL,
-                  TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg)
+                  TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
                   .addReg(TmpReg, RegState::Kill)
-                  .addImm(0)
                   .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
         }
       }
 
       // TODO: only do this when it is needed
       switch (MF->getSubtarget<AMDGPUSubtarget>().getGeneration()) {
       case AMDGPUSubtarget::SOUTHERN_ISLANDS:
         // "VALU writes SGPR" -> "SMRD reads that SGPR" needs 4 wait states