[mips][ias] Move createCpRestoreMemOp to MipsTargetStreamer. NFC.

[dsanders]

Summary

This removes the temporary call to isIntegratedAssemblerRequired() which was
added recently. It's effect is now acheived directly in the MipsTargetStreamer
hierarchy.

Depends on D19714.

[sdardis]

LGTM.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

if (IsCpRestoreSet) {
       // We need a NOP between the JALR and the LW:
       // If .set reorder has been used, we've already emitted a NOP.
       // If .set noreorder has been used, we need to emit a NOP at this point.
       if (!AssemblerOptions.back()->isReorder())
         TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst.getOpcode()), IDLoc,
                                 STI);
 
       // Load the $gp from the stack.
-      createCpRestoreMemOp(true /*IsLoad*/, CpRestoreOffset /*StackOffset*/,
-                           IDLoc, Out, STI);
+      TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI);
     } else
       Warning(IDLoc, "no .cprestore used in PIC mode");
   }
 
   return false;
 }
 
 MipsAsmParser::MacroExpanderResultTy
bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   return false;
 }
 
 void MipsAsmParser::createCpRestoreMemOp(bool IsLoad, int StackOffset,
                                          SMLoc IDLoc, MCStreamer &Out,
                                          const MCSubtargetInfo *STI) {
   MipsTargetStreamer &TOut = getTargetStreamer();
 
-  // If the offset can not fit into 16 bits, we need to expand.
-  if (!isInt<16>(StackOffset)) {
-    MCInst MemInst;
-    MemInst.setOpcode(IsLoad ? Mips::LW : Mips::SW);
-    MemInst.addOperand(MCOperand::createReg(Mips::GP));
-    MemInst.addOperand(MCOperand::createReg(Mips::SP));
-    MemInst.addOperand(MCOperand::createImm(StackOffset));
-    expandMemInst(MemInst, IDLoc, Out, STI, IsLoad, true /*HasImmOpnd*/);
+  if (IsLoad) {
+    TOut.emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, StackOffset,
+                               Mips::GP, IDLoc, STI);
     return;
   }
 
-  TOut.emitRRI(IsLoad ? Mips::LW : Mips::SW, Mips::GP, Mips::SP, StackOffset,
+  unsigned ATReg = getATReg(IDLoc);
+  if (!ATReg)
+    return;
+
+  TOut.emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, StackOffset, ATReg,
                               IDLoc, STI);
 }
 
 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   // As described by the Mips32r2 spec, the registers Rd and Rs for
   // jalr.hb must be different.
   // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
   unsigned Opcode = Inst.getOpcode();
 
bool MipsAsmParser::parseDirectiveCpRestore(SMLoc Loc) {
   }
 
   // If this is not the end of the statement, report an error.
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     reportParseError("unexpected token, expected end of statement");
     return false;
   }
 
-  // Store the $gp on the stack.
-  if (getStreamer().isIntegratedAssemblerRequired()) {
-    const MCSubtargetInfo &STI = getSTI();
-    createCpRestoreMemOp(false /*IsLoad*/, CpRestoreOffset /*StackOffset*/, Loc,
-                         getStreamer(), &STI);
-  }
+  unsigned ATReg = getATReg(Loc);
+  if (!ATReg)
+    return true;
 
-  getTargetStreamer().emitDirectiveCpRestore(CpRestoreOffset);
+  getTargetStreamer().emitDirectiveCpRestore(CpRestoreOffset, ATReg, Loc, STI);
   Parser.Lex(); // Consume the EndOfStatement.
   return false;
 }
 
 bool MipsAsmParser::parseDirectiveCPSetup() {
   MCAsmParser &Parser = getParser();
   unsigned FuncReg;
   unsigned Save;

lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
   forbidModuleDirective();
 }
 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
   forbidModuleDirective();
 }
 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
-void MipsTargetStreamer::emitDirectiveCpRestore(int Offset) {
+void MipsTargetStreamer::emitDirectiveCpRestore(int Offset, unsigned ATReg,
+                                                SMLoc IDLoc,
+                                                const MCSubtargetInfo *STI) {
   forbidModuleDirective();
 }
 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                                               const MCSymbol &Sym, bool IsReg) {
 }
 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
                                                bool SaveLocationIsRegister) {}
 
void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
   else
     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
 }
 
 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
   emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
 }
 
-/// Emit a store instruction with an immediate offset. The immediate is
-/// expected to be out-of-range for a simm16 and will be expanded to
-/// appropriate instructions.
+/// Emit the $gp restore operation for .cprestore.
+void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
+                                       const MCSubtargetInfo *STI) {
+  emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
+                        STI);
+}
+
+/// Emit a store instruction with an immediate offset.
 void MipsTargetStreamer::emitStoreWithImmOffset(
     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
     unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) {
+  if (isInt<16>(Offset)) {
+    emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
+    return;
+  }
+
   // sw $8, offset($8) => lui $at, %hi(offset)
   //                      add $at, $at, $8
   //                      sw $8, %lo(offset)($at)
 
   unsigned LoOffset = Offset & 0x0000ffff;
   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
 
   // If msb of LoOffset is 1(negative number) we must increment HiOffset
void MipsTargetStreamer::emitStoreWithSymOffset(
   // Generate the base address in ATReg.
   emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
   if (BaseReg != Mips::ZERO)
     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
   // Emit the store with the adjusted base and offset.
   emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
 }
 
-/// Emit a load instruction with an immediate offset. The immediate is expected
-/// to be out-of-range for a simm16 and will be expanded to appropriate
-/// instructions. DstReg and TmpReg are permitted to be the same register iff
-/// DstReg is distinct from BaseReg and DstReg is a GPR. It is the callers
-/// responsibility to identify such cases and pass the appropriate register in
-/// TmpReg.
+/// Emit a load instruction with an immediate offset. DstReg and TmpReg are
+/// permitted to be the same register iff DstReg is distinct from BaseReg and
+/// DstReg is a GPR. It is the callers responsibility to identify such cases
+/// and pass the appropriate register in TmpReg.
 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
                                                unsigned BaseReg, int64_t Offset,
                                                unsigned TmpReg, SMLoc IDLoc,
                                                const MCSubtargetInfo *STI) {
+  if (isInt<16>(Offset)) {
+    emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
+    return;
+  }
+
   // 1) lw $8, offset($9) => lui $8, %hi(offset)
   //                         add $8, $8, $9
   //                         lw $8, %lo(offset)($9)
   // 2) lw $8, offset($8) => lui $at, %hi(offset)
   //                         add $at, $at, $8
   //                         lw $8, %lo(offset)($at)
 
   unsigned LoOffset = Offset & 0x0000ffff;

 }
 
 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
   OS << "\t.cpload\t$"
      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
   forbidModuleDirective();
 }
 
-void MipsTargetAsmStreamer::emitDirectiveCpRestore(int Offset) {
-  MipsTargetStreamer::emitDirectiveCpRestore(Offset);
+void MipsTargetAsmStreamer::emitDirectiveCpRestore(int Offset, unsigned ATReg,
+                                                   SMLoc IDLoc,
+                                                   const MCSubtargetInfo *STI) {
+  MipsTargetStreamer::emitDirectiveCpRestore(Offset, ATReg, IDLoc, STI);
   OS << "\t.cprestore\t" << Offset << "\n";
 }
 
 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
                                                  int RegOrOffset,
                                                  const MCSymbol &Sym,
                                                  bool IsReg) {
   OS << "\t.cpsetup\t$"
void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
   TmpInst.addOperand(MCOperand::createReg(RegNo));
   getStreamer().EmitInstruction(TmpInst, STI);
 
   forbidModuleDirective();
 }
 
-void MipsTargetELFStreamer::emitDirectiveCpRestore(int Offset) {
-  MipsTargetStreamer::emitDirectiveCpRestore(Offset);
+void MipsTargetELFStreamer::emitDirectiveCpRestore(int Offset, unsigned ATReg,
+                                                   SMLoc IDLoc,
+                                                   const MCSubtargetInfo *STI) {
+  MipsTargetStreamer::emitDirectiveCpRestore(Offset, ATReg, IDLoc, STI);
   // .cprestore offset
   // When PIC mode is enabled and the O32 ABI is used, this directive expands
   // to:
   //    sw $gp, offset($sp)
   // and adds a corresponding LW after every JAL.
 
   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
   // is used in non-PIC mode.
   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
     return;
 
-  // FIXME: MipsAsmParser currently emits the instructions that should be
-  // emitted here.
+  // Store the $gp on the stack.
+  emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, ATReg, IDLoc,
+                         STI);
 }
 
 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
                                                  int RegOrOffset,
                                                  const MCSymbol &Sym,
                                                  bool IsReg) {
   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))

lib/Target/Mips/MipsTargetStreamer.h

public:
   virtual void emitDirectiveSetNoDsp();
   virtual void emitDirectiveSetPop();
   virtual void emitDirectiveSetPush();
   virtual void emitDirectiveSetSoftFloat();
   virtual void emitDirectiveSetHardFloat();
 
   // PIC support
   virtual void emitDirectiveCpLoad(unsigned RegNo);
-  virtual void emitDirectiveCpRestore(int Offset);
+  virtual void emitDirectiveCpRestore(int Offset, unsigned ATReg, SMLoc IDLoc,
+                                      const MCSubtargetInfo *STI);
   virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                                     const MCSymbol &Sym, bool IsReg);
   virtual void emitDirectiveCpreturn(unsigned SaveLocation,
                                      bool SaveLocationIsRegister);
 
   // FP abiflags directives
   virtual void emitDirectiveModuleFP();
   virtual void emitDirectiveModuleOddSPReg();
void emitStoreWithSymOffset(unsigned Opcode, unsigned SrcReg,
                               const MCSubtargetInfo *STI);
   void emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg,
                              int64_t Offset, unsigned TmpReg, SMLoc IDLoc,
                              const MCSubtargetInfo *STI);
   void emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg, unsigned BaseReg,
                              MCOperand &HiOperand, MCOperand &LoOperand,
                              unsigned ATReg, SMLoc IDLoc,
                              const MCSubtargetInfo *STI);
+  void emitGPRestore(int Offset, SMLoc IDLoc, const MCSubtargetInfo *STI);
 
   void forbidModuleDirective() { ModuleDirectiveAllowed = false; }
   void reallowModuleDirective() { ModuleDirectiveAllowed = true; }
   bool isModuleDirectiveAllowed() { return ModuleDirectiveAllowed; }
 
   // This method enables template classes to set internal abi flags
   // structure values.
   template <class PredicateLibrary>
public:
   void emitDirectiveSetNoDsp() override;
   void emitDirectiveSetPop() override;
   void emitDirectiveSetPush() override;
   void emitDirectiveSetSoftFloat() override;
   void emitDirectiveSetHardFloat() override;
 
   // PIC support
   void emitDirectiveCpLoad(unsigned RegNo) override;
-  void emitDirectiveCpRestore(int Offset) override;
+  void emitDirectiveCpRestore(int Offset, unsigned ATReg, SMLoc IDLoc,
+                              const MCSubtargetInfo *STI) override;
   void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                             const MCSymbol &Sym, bool IsReg) override;
   void emitDirectiveCpreturn(unsigned SaveLocation,
                              bool SaveLocationIsRegister) override;
 
   // FP abiflags directives
   void emitDirectiveModuleFP() override;
   void emitDirectiveModuleOddSPReg() override;
public:
   void emitDirectiveInsn() override;
   void emitFrame(unsigned StackReg, unsigned StackSize,
                  unsigned ReturnReg) override;
   void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
   void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
 
   // PIC support
   void emitDirectiveCpLoad(unsigned RegNo) override;
-  void emitDirectiveCpRestore(int Offset) override;
+  void emitDirectiveCpRestore(int Offset, unsigned ATReg, SMLoc IDLoc,
+                              const MCSubtargetInfo *STI) override;
   void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                             const MCSymbol &Sym, bool IsReg) override;
   void emitDirectiveCpreturn(unsigned SaveLocation,
                              bool SaveLocationIsRegister) override;
 
   void emitMipsAbiFlags();
 };
 }
 #endif

test/MC/Mips/double-expand.s

 # RUN: llvm-mc -triple=mipsel-unknown-linux < %s | FileCheck %s
 # RUN: llvm-mc -triple=mipsel-unknown-linux < %s | \
 # RUN:     llvm-mc -triple=mipsel-unknown-linux | FileCheck %s
 
-# CHECK: bnez $2, foo
-# CHECK: nop
-# CHECK-NOT: nop
+        .text
+branch:
+  bnez $2, foo
+
+# CHECK-LABEL: branch:
+# CHECK:           bnez $2, foo
+# CHECK:           nop
+# CHECK-NOT:       nop
 
-        .text
-  bnez $2, foo
+cprestore:
+  .option pic2
+  .cprestore 16
+  jal foo
+
+# CHECK-LABEL: cprestore:
+# CHECK:           .cprestore 16
+# CHECK:           lw $25, %call16(foo)($gp)
+# CHECK:           jalr $25
+# CHECK:           nop
+# CHECK:           lw $gp, 16($sp)
+# CHECK-NOT:       nop
+# CHECK-NOT:       lw