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Differential D19568

[X86] Replace -mcpu with -mattr in several tests
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Authored by mbodart on Apr 26 2016, 4:28 PM.

Details

Reviewers
spatel
Commits
rL267629: [X86] Replace -mcpu with -mattr in several tests
Summary

In preparation for the scheduling changes in D19138, eliminate unnecessary use of -mcpu in several tests,
replacing it with -mattr=+sse2 where relevant (the tests use SSE2 instructions), or simply removing it.

This allows the tests to pass with or without the D19138 changes.

Diff Detail

Event Timeline

mbodart updated this revision to Diff 55118.Apr 26 2016, 4:28 PM
mbodart retitled this revision from to [X86] Replace -mcpu with -mattr in several tests.
mbodart updated this object.
mbodart added a reviewer: spatel.
mbodart added a subscriber: llvm-commits.
spatel accepted this revision.Apr 26 2016, 4:33 PM
spatel edited edge metadata.

LGTM.
Thank you for the clean up. Feel free to check in this kind of change without pre-commit review. :)

This revision is now accepted and ready to land.Apr 26 2016, 4:33 PM
mbodart mentioned this in D19138: [X86] Enable the post-RA-scheduler for 32-bit cpus.Apr 26 2016, 4:36 PM
Closed by commit rL267629: [X86] Replace -mcpu with -mattr in several tests (authored by mbodart). · Explain WhyApr 26 2016, 4:42 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
test/
CodeGen/
X86/
2 lines
4 lines
2 lines
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Diff 55118

test/CodeGen/X86/machine-cp.ll

; RUN: llc -mtriple=x86_64-apple-macosx -mcpu=nocona -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-apple-macosx -mattr=+sse2 -verify-machineinstrs < %s | FileCheck %s
; After tail duplication, two copies in an early exit BB can be cancelled out. ; After tail duplication, two copies in an early exit BB can be cancelled out.
; rdar://10640363 ; rdar://10640363
define i32 @t1(i32 %a, i32 %b) nounwind { define i32 @t1(i32 %a, i32 %b) nounwind {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: je [[LABEL:.*BB.*]] ; CHECK: je [[LABEL:.*BB.*]]
%cmp1 = icmp eq i32 %b, 0 %cmp1 = icmp eq i32 %b, 0
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test/CodeGen/X86/misched-ilp.ll

; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=nocona -enable-misched -misched=ilpmax | FileCheck -check-prefix=MAX %s ; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+sse2 -enable-misched -misched=ilpmax | FileCheck -check-prefix=MAX %s
; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=nocona -enable-misched -misched=ilpmin | FileCheck -check-prefix=MIN %s ; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+sse2 -enable-misched -misched=ilpmin | FileCheck -check-prefix=MIN %s
; ;
; Basic verification of the ScheduleDAGILP metric. ; Basic verification of the ScheduleDAGILP metric.
; ;
; MAX: addss ; MAX: addss
; MAX: addss ; MAX: addss
; MAX: addss ; MAX: addss
; MAX: subss ; MAX: subss
; MAX: addss ; MAX: addss
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test/CodeGen/X86/pr16360.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=pentium4 -mtriple=i686-pc-linux | FileCheck %s ; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s
define i64 @foo(i32 %sum) { define i64 @foo(i32 %sum) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: shrl $2, %eax ; CHECK-NEXT: shrl $2, %eax
; CHECK-NEXT: orl $-67108864, %eax # imm = 0xFFFFFFFFFC000000 ; CHECK-NEXT: orl $-67108864, %eax # imm = 0xFFFFFFFFFC000000
; CHECK-NEXT: movl $1073741823, %edx # imm = 0x3FFFFFFF ; CHECK-NEXT: movl $1073741823, %edx # imm = 0x3FFFFFFF
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%conv = sext i32 %sum to i64 %conv = sext i32 %sum to i64
%shr = lshr i64 %conv, 2 %shr = lshr i64 %conv, 2
%or = or i64 4611686018360279040, %shr %or = or i64 4611686018360279040, %shr
ret i64 %or ret i64 %or
} }

test/CodeGen/X86/sse2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Tests for SSE2 and below, without SSE3+. ; Tests for SSE2 and below, without SSE3+.
; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 -O3 | FileCheck %s ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+sse2 -O3 | FileCheck %s
define void @test1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { define void @test1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movapd (%ecx), %xmm0 ; CHECK-NEXT: movapd (%ecx), %xmm0
; CHECK-NEXT: movlpd {{.*#+}} xmm0 = mem[0],xmm0[1] ; CHECK-NEXT: movlpd {{.*#+}} xmm0 = mem[0],xmm0[1]
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