- User Since
- Jul 17 2015, 11:41 AM (209 w, 3 d)
May 26 2016
Thanks for the .mir suggestions!
I uploaded the alternate fix I alluded to, which is all in ScanInstruction.
This retains the KeepReg setting from Sanjay's fix for pr20020, but performs the other liveness updates.
In particular, DefIndices[%CH] gets updated, and prevents %CH from being used as a replacement register.
May 25 2016
Sanjay, I tried backing out your fix for pr20020.ll, but the test passes either way. So something else changed along the way.
This is a great argument for using a .mir test, and I'll pursue that.
May 24 2016
I wasn't familiar with .mir files, so thanks for pointing them out!
Unfortunately creating one directly from the original pr27681.ll file yields
a .mir file which incurs various parse and semantic errors when run through
llc, so it may take some effort to get a clean .mir file. Perhaps someone
with more experience than I can whip one out quickly?
May 23 2016
I was also not familiar with this code, until diving in to fix pr27681.
May 20 2016
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Apr 27 2016
Thanks for the testing suggestions Sanjay, but I think I'll stick with the current test for now.
Rebased, and removed several lit tests from this change set as I updated them separately.
Apr 26 2016
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Apr 1 2016
Unfortunately the tuning I had planned in isFormingBranchFromSelectProfitable is no longer applicable.
The relevant heuristic was the "load feeding compare", which I intended to relax a bit.
Per discussions in other code reviews in that area (I don't have the number off hand, but maybe
related to D16836 and D17288), that heurstic has been deleted altogether, and there seemed to be a
general consensus to move this transformation into the target.
Feb 17 2016
I'm looking into resurrecting the nonlocal dead store elimination in http://reviews.llvm.org/D13363,
but one of the snags is a performance issue related to select-vs-branch choices. That change enables
more selects, which unfortunately incur a 10 to 20% perf drop on some benchmarks in the EEMBC automotive
suite, on various X86 architectures.
Feb 16 2016
Added individual CHECK-LABEL's per function, per review feedback.
Feb 9 2016
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Jan 22 2016
I have a resolution for the issue causing bot timeouts,
as well as one unrelated fix for irreducible control flow.
Fortunately both fixes are trivial. Details below.
Jan 21 2016
Thanks for the explanations (and patience)!
Jan 19 2016
Oops! Thanks for pointing that out Asaf.
Jan 14 2016
I'm not sure I understand why this is just now becoming an issue.
Jan 8 2016
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Nov 9 2015
The changes look good, but I have a couple questions on the requirements of soft float support.
Nov 6 2015
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Oct 13 2015
In general I think your approach of using a reverse CFG search for this optimization is appropriate. But as Erik points out it doesn't handle if-then-else.
That can be addressed relatively easily:
Oct 1 2015
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Aug 17 2015
Updated new test to use -mattr instead of -mcpu, per MK's recommendation.
Aug 10 2015
Applied fixes for David's recent comments (using ANY_EXTEND, and formatting).
I uploaded a new revision, removing all usage of isTargetFTOL and isIntegerTypeFTOL, which I think is sufficient for this change set. I left the WIN_FTOL instructions, as conceivably those could still be used for conversion to signed int64, though they aren't currently.
Aug 2 2015
Jul 30 2015
Per Michael Spencer's suggestion, added Nadav as a reviewer.
Jul 27 2015