Page MenuHomePhabricator

Sparc itineraries support, with LEON3 and LEON4 itineraries added
ClosedPublic

Authored by lero_chris on Apr 21 2016, 5:14 AM.

Details

Summary

This provides support for itineraries on Sparc.

Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.

The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.

As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.

Diff Detail

Repository
rL LLVM

Event Timeline

lero_chris updated this revision to Diff 54487.Apr 21 2016, 5:14 AM
lero_chris retitled this revision from to Sparc itineraries support, with LEON3 and LEON4 itineraries added.
lero_chris updated this object.
lero_chris set the repository for this revision to rL LLVM.
jyknight edited edge metadata.May 4 2016, 6:41 AM

Some test case showing a reordering arising from the instruction latency info would be good.

Also, I'd really like if someone more familiar with scheduling could say whether using InstrItin{Class/Data} is okay to use for new code, or if it should be reworked using the SchedMachineModel scheme. I'm not sure at this point whether the latter should always be used in preference to the former.

Anyone care to comment about that?

lero_chris updated this revision to Diff 56586.May 9 2016, 9:03 AM
lero_chris edited edge metadata.

Added unit tests covering changing instruction ordering due to different itineraries for LEON processors.

lero_chris accepted this revision.May 12 2016, 12:31 PM
lero_chris added a reviewer: lero_chris.
This revision is now accepted and ready to land.May 12 2016, 12:31 PM
lero_chris closed this revision.May 12 2016, 12:31 PM

Closing, due to lack on new comments. Changes are working as planned.