[AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.

[artem.tamazov]

Summary

Added hwreg(reg[,offset,width]) syntax.
Default offset = 0, default width = 32.
Possibility to specify 16-bit immediate kept.
Added out-of-range checks.
Disassembly is always to hwreg(...) format.
Tests updated/added.

[artem.tamazov]

Ping...

[arsenm]

LGTM. Were there symbolic names for these? I think I've seen them in dumps before

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

764 ↗

(On Diff #54379)

Indentation looks off

[artem.tamazov]

lndentation fixed.

[nhaustov]

Ok.

[artem.tamazov]

Somehow forgotten CodeGen test updated

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

enum ImmTy {
     ImmTyDppRowMask,
     ImmTyDppBankMask,
     ImmTyDppBoundCtrl,
     ImmTyDMask,
     ImmTyUNorm,
     ImmTyDA,
     ImmTyR128,
     ImmTyLWE,
+    ImmTyHwreg,
   };
 
   struct TokOp {
     const char *Data;
     unsigned Length;
   };
 
   struct ImmOp {
static std::unique_ptr<AMDGPUOperand> CreateExpr(const class MCExpr *Expr, SMLoc S) {
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;
   }
 
   bool isDSOffset() const;
   bool isDSOffset01() const;
   bool isSWaitCnt() const;
+  bool isHwreg() const;
   bool isMubufOffset() const;
   bool isSMRDOffset() const;
   bool isSMRDLiteralOffset() const;
   bool isDPPCtrl() const;
 };
 
 class AMDGPUAsmParser : public MCTargetAsmParser {
   const MCInstrInfo &MII;
public:
   void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
   void cvtDS(MCInst &Inst, const OperandVector &Operands);
   OperandMatchResultTy parseDSOptionalOps(OperandVector &Operands);
   OperandMatchResultTy parseDSOff01OptionalOps(OperandVector &Operands);
   OperandMatchResultTy parseDSOffsetOptional(OperandVector &Operands);
 
   bool parseCnt(int64_t &IntVal);
   OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
+  bool parseHwreg(int64_t &HwRegCode, int64_t &Offset, int64_t &Width);
+  OperandMatchResultTy parseHwregOp(OperandVector &Operands);
   OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
 
   OperandMatchResultTy parseFlatOptionalOps(OperandVector &Operands);
   OperandMatchResultTy parseFlatAtomicOptionalOps(OperandVector &Operands);
   void cvtFlat(MCInst &Inst, const OperandVector &Operands);
   void cvtFlatAtomic(MCInst &Inst, const OperandVector &Operands);
 
   void cvtMubuf(MCInst &Inst, const OperandVector &Operands);
case AsmToken::Identifier:
           return MatchOperand_ParseFail;
       } while(getLexer().isNot(AsmToken::EndOfStatement));
       break;
   }
   Operands.push_back(AMDGPUOperand::CreateImm(CntVal, S));
   return MatchOperand_Success;
 }
 
+bool AMDGPUAsmParser::parseHwreg(int64_t &HwRegCode, int64_t &Offset, int64_t &Width) {
+  if (Parser.getTok().getString() != "hwreg")
+    return true;
+  Parser.Lex();
+
+  if (getLexer().isNot(AsmToken::LParen))
+    return true;
+  Parser.Lex();
+
+  if (getLexer().isNot(AsmToken::Integer))
+    return true;
+  if (getParser().parseAbsoluteExpression(HwRegCode))
+    return true;
+
+  if (getLexer().is(AsmToken::RParen)) {
+    Parser.Lex();
+    return false;
+  }
+
+  // optional params
+  if (getLexer().isNot(AsmToken::Comma))
+    return true;
+  Parser.Lex();
+
+  if (getLexer().isNot(AsmToken::Integer))
+    return true;
+  if (getParser().parseAbsoluteExpression(Offset))
+    return true;
+
+  if (getLexer().isNot(AsmToken::Comma))
+    return true;
+  Parser.Lex();
+
+  if (getLexer().isNot(AsmToken::Integer))
+    return true;
+  if (getParser().parseAbsoluteExpression(Width))
+    return true;
+
+  if (getLexer().isNot(AsmToken::RParen))
+    return true;
+  Parser.Lex();
+
+  return false;
+}
+
+AMDGPUAsmParser::OperandMatchResultTy
+AMDGPUAsmParser::parseHwregOp(OperandVector &Operands) {
+  int64_t Imm16Val = 0;
+  SMLoc S = Parser.getTok().getLoc();
+
+  switch(getLexer().getKind()) {
+    default: return MatchOperand_ParseFail;
+    case AsmToken::Integer:
+      // The operand can be an integer value.
+      if (getParser().parseAbsoluteExpression(Imm16Val))
+        return MatchOperand_ParseFail;
+      if (!isInt<16>(Imm16Val) && !isUInt<16>(Imm16Val)) {
+        Error(S, "invalid immediate: only 16-bit values are legal");
+        // Do not return error code, but create an imm operand anyway and proceed
+        // to the next operand, if any. That avoids unneccessary error messages.
+      }
+      break;
+
+    case AsmToken::Identifier: {
+        int64_t HwRegCode = 0;
+        int64_t Offset = 0; // default
+        int64_t Width = 32; // default
+        if (parseHwreg(HwRegCode, Offset, Width))
+          return MatchOperand_ParseFail;
+        // HwRegCode (6) [5:0]
+        // Offset (5) [10:6]
+        // WidthMinusOne (5) [15:11]
+        if (HwRegCode < 0 || HwRegCode > 63)
+          Error(S, "invalid code of hardware register: only 6-bit values are legal");
+        if (Offset < 0 || Offset > 31)
+          Error(S, "invalid bit offset: only 5-bit values are legal");
+        if (Width < 1 || Width > 32)
+          Error(S, "invalid bitfield width: only values from 1 to 32 are legal");
+        Imm16Val = HwRegCode | (Offset << 6) | ((Width-1) << 11);
+      }
+      break;
+  }
+  Operands.push_back(AMDGPUOperand::CreateImm(Imm16Val, S, AMDGPUOperand::ImmTyHwreg));
+  return MatchOperand_Success;
+}
+
 bool AMDGPUOperand::isSWaitCnt() const {
   return isImm();
 }
 
+bool AMDGPUOperand::isHwreg() const {
+  return isImmTy(ImmTyHwreg);
+}
+
 //===----------------------------------------------------------------------===//
 // sopp branch targets
 //===----------------------------------------------------------------------===//
 
 AMDGPUAsmParser::OperandMatchResultTy
 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
   SMLoc S = Parser.getTok().getLoc();
 

llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h

private:
   static void printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   static void printSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   static void printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   static void printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   static void printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   static void printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   static void printSendMsg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   static void printWaitFlag(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  static void printHwreg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 };
 
 } // End namespace llvm
 
 #endif

llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
 
   if (Lgkmcnt != 0xF) {
     if (NeedSpace)
       O << ' ';
     O << "lgkmcnt(" << Lgkmcnt << ')';
   }
 }
 
+void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
+                                   raw_ostream &O) {
+  unsigned SImm16 = MI->getOperand(OpNo).getImm();
+  const unsigned HwRegCode = SImm16 & 0x3F;
+  const unsigned Offset = (SImm16 >> 6) & 0x1f;
+  const unsigned Width = ((SImm16 >> 11) & 0x1F) + 1;
+
+  if (Width == 32 && Offset == 0) {
+    O << "hwreg(" << HwRegCode << ')';
+  } else {
+    O << "hwreg(" << HwRegCode << ", " << Offset << ", " << Width << ')';
+  }
+}
+
 #include "AMDGPUGenAsmWriter.inc"

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

class NamedBitMatchClass<string BitName> : AsmOperandClass {
   let RenderMethod = "addImmOperands";
   let IsOptional = 1;
 }
 
 class NamedBitOperand<string BitName> : Operand<i1> {
   let PrintMethod = "print"#BitName;
 }
 
+def HwregMatchClass : AsmOperandClass {
+  let Name = "Hwreg";
+  let PredicateMethod = "isHwreg";
+  let ParserMethod = "parseHwregOp";
+  let RenderMethod = "addImmOperands";
+}
+
 let OperandType = "OPERAND_IMMEDIATE" in {
 
 def offen : Operand<i1> {
   let PrintMethod = "printOffen";
   let ParserMatchClass = OptionalImmAsmOperand<"offen">;
 }
 def idxen : Operand<i1> {
   let PrintMethod = "printIdxen";
def bank_mask : Operand <i32> {
   let ParserMatchClass = DPPOptionalMatchClass<"BankMask">;
 }
 
 def bound_ctrl : Operand <i1> {
   let PrintMethod = "printBoundCtrlOperand";
   let ParserMatchClass = DPPOptionalMatchClass<"BoundCtrl">;
 }
 
+def hwreg : Operand <i16> {
+  let PrintMethod = "printHwreg";
+  let ParserMatchClass = HwregMatchClass;
+}
+
 } // End OperandType = "OPERAND_IMMEDIATE"
 
 
 def VOPDstS64 : VOPDstOperand <SReg_64>;
 
 //===----------------------------------------------------------------------===//
 // Complex patterns
 //===----------------------------------------------------------------------===//

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

 }
 
 defm S_CBRANCH_I_FORK : SOPK_m <
   sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs),
   (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16"
 >;
 
 let mayLoad = 1 in {
-defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>;
+defm S_GETREG_B32 : SOPK_m <
+  sopk<0x12, 0x11>, "s_getreg_b32", (outs SReg_32:$sdst),
+  (ins hwreg:$simm16), " $sdst, $simm16"
+>;
 }
 
 defm S_SETREG_B32 : SOPK_m <
   sopk<0x13, 0x12>, "s_setreg_b32", (outs),
-  (ins SReg_32:$sdst, u16imm:$simm16), " $simm16, $sdst"
+  (ins SReg_32:$sdst, hwreg:$simm16), " $simm16, $sdst"
 >;
 // FIXME: Not on SI?
 //defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>;
 defm S_SETREG_IMM32_B32 : SOPK_IMM32 <
   sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs),
-  (ins i32imm:$imm, u16imm:$simm16), " $simm16, $imm"
+  (ins i32imm:$imm, hwreg:$simm16), " $simm16, $imm"
 >;
 
 //===----------------------------------------------------------------------===//
 // SOPP Instructions
 //===----------------------------------------------------------------------===//
 
 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
 

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll

 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
 
 ; FUNC-LABEL: {{^}}s_getreg_test:
-; CHECK: s_getreg_b32 s{{[0-9]+}}, 0xb206
+; CHECK: s_getreg_b32 s{{[0-9]+}}, hwreg(6, 8, 23)
 define void @s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds size.
   %lds_size_64dwords = call i32 @llvm.amdgcn.s.getreg(i32 45574) #0
   %lds_size_bytes = shl i32 %lds_size_64dwords, 8
   store i32 %lds_size_bytes, i32 addrspace(1)* %out
   ret void
 }
 
 declare i32 @llvm.amdgcn.s.getreg(i32) #0
 
 attributes #0 = { nounwind readonly}

llvm/trunk/test/MC/AMDGPU/sopk-err.s

+// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+s_setreg_b32  0x1f803, s2
+// GCN: error: invalid immediate: only 16-bit values are legal
+
+s_setreg_b32  hwreg(0x40), s2
+// GCN: error: invalid code of hardware register: only 6-bit values are legal
+
+s_setreg_b32  hwreg(3,32,32), s2
+// GCN: error: invalid bit offset: only 5-bit values are legal
+
+s_setreg_b32  hwreg(3,0,33), s2
+// GCN: error: invalid bitfield width: only values from 1 to 32 are legal
+
+s_setreg_imm32_b32  0x1f803, 0xff
+// GCN: error: invalid immediate: only 16-bit values are legal
+
+s_setreg_imm32_b32  hwreg(3,0,33), 0xff
+// GCN: error: invalid bitfield width: only values from 1 to 32 are legal
+
+s_getreg_b32  s2, hwreg(3,32,32)
+// GCN: error: invalid bit offset: only 5-bit values are legal

llvm/trunk/test/MC/AMDGPU/sopk.s

 // SICI: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
 // VI:   s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
 
 s_cbranch_i_fork s[2:3], 0x6
 // SICI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
 // VI:   s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
 
 s_getreg_b32 s2, 0x6
-// SICI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9]
-// VI:   s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
+// SICI: s_getreg_b32 s2, hwreg(6, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
+// VI:   s_getreg_b32 s2, hwreg(6, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]
+
+s_getreg_b32 s2, hwreg(5, 1, 31)
+// SICI: s_getreg_b32 s2, hwreg(5, 1, 31) ; encoding: [0x45,0xf0,0x02,0xb9]
+// VI:   s_getreg_b32 s2, hwreg(5, 1, 31) ; encoding: [0x45,0xf0,0x82,0xb8]
 
 s_setreg_b32 0x6, s2
-// SICI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x82,0xb9]
-// VI:   s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9]
+// SICI: s_setreg_b32 hwreg(6, 0, 1), s2 ; encoding: [0x06,0x00,0x82,0xb9]
+// VI:   s_setreg_b32 hwreg(6, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]
+
+s_setreg_b32 0xf803, s2
+// SICI: s_setreg_b32 hwreg(3), s2       ; encoding: [0x03,0xf8,0x82,0xb9]
+// VI:   s_setreg_b32 hwreg(3), s2       ; encoding: [0x03,0xf8,0x02,0xb9]
+
+s_setreg_b32 hwreg(4), s2
+// SICI: s_setreg_b32 hwreg(4), s2       ; encoding: [0x04,0xf8,0x82,0xb9]
+// VI:   s_setreg_b32 hwreg(4), s2       ; encoding: [0x04,0xf8,0x02,0xb9]
+
+s_setreg_b32 hwreg(5, 1, 31), s2
+// SICI: s_setreg_b32 hwreg(5, 1, 31), s2       ; encoding: [0x45,0xf0,0x82,0xb9]
+// VI:   s_setreg_b32 hwreg(5, 1, 31), s2       ; encoding: [0x45,0xf0,0x02,0xb9]
 
 s_setreg_imm32_b32 0x6, 0xff
-// SICI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
-// VI:   s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
+// SICI: s_setreg_imm32_b32 hwreg(6, 0, 1), 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
+// VI:   s_setreg_imm32_b32 hwreg(6, 0, 1), 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
+
+s_setreg_imm32_b32 hwreg(5, 1, 31), 0xff
+// SICI: s_setreg_imm32_b32 hwreg(5, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]
+// VI:   s_setreg_imm32_b32 hwreg(5, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]

llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt

 0x06 0x00 0x02 0xb7
 
 # VI:   s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
 0x06 0x00 0x82 0xb7
 
 # VI:   s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
 0x06 0x00 0x02 0xb8
 
-# VI:   s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
-0x06 0x00 0x82 0xb8
+# VI:   s_getreg_b32 s2, hwreg(6) ; encoding: [0x06,0xf8,0x82,0xb8]
+0x06 0xf8 0x82 0xb8
 
-# VI:   s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9]
+# VI:   s_setreg_b32 hwreg(6, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]
 0x06 0x00 0x02 0xb9
 
-# VI:   s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
-0x06 0x00 0x00 0xba 0xff 0x00 0x00 0x00
+# VI:   s_setreg_imm32_b32 hwreg(5, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
+0x45 0xf0 0x00 0xba 0xff 0x00 0x00 0x00