[PATCH] [Mips] [MSan] VarArgMIPS64Helper: Use target's endian, not host's.

[• koriakin]

Summary

Ugh.

[eugenis]

Ouch.
LGTM

[aizatsky]

Can you create a test?

[• koriakin]

In D19292#405986, @aizatsky wrote:

Can you create a test?

I'll try, but I don't know all that much about MIPS (I was looking at the code because I'm writing a vararg helper for PPC64).

llvm/trunk/lib/Transforms/Instrumentation/MemorySanitizer.cpp

VarArgMIPS64Helper(Function &F, MemorySanitizer &MS,
     : F(F), MS(MS), MSV(MSV), VAArgTLSCopy(nullptr),
       VAArgSize(nullptr) {}
 
   void visitCallSite(CallSite &CS, IRBuilder<> &IRB) override {
     unsigned VAArgOffset = 0;
     const DataLayout &DL = F.getParent()->getDataLayout();
     for (CallSite::arg_iterator ArgIt = CS.arg_begin() + 1, End = CS.arg_end();
          ArgIt != End; ++ArgIt) {
+      llvm::Triple TargetTriple(F.getParent()->getTargetTriple());
       Value *A = *ArgIt;
       Value *Base;
       uint64_t ArgSize = DL.getTypeAllocSize(A->getType());
-#if defined(__MIPSEB__) || defined(MIPSEB)
+      if (TargetTriple.getArch() == llvm::Triple::mips64) {
         // Adjusting the shadow for argument with size < 8 to match the placement
         // of bits in big endian system
         if (ArgSize < 8)
           VAArgOffset += (8 - ArgSize);
-#endif
+      }
       Base = getShadowPtrForVAArgument(A->getType(), IRB, VAArgOffset);
       VAArgOffset += ArgSize;
       VAArgOffset = alignTo(VAArgOffset, 8);
       IRB.CreateAlignedStore(MSV.getShadow(A), Base, kShadowTLSAlignment);
     }
 
     Constant *TotalVAArgSize = ConstantInt::get(IRB.getInt64Ty(), VAArgOffset);
     // Here using VAArgOverflowSizeTLS as VAArgSizeTLS to avoid creation of