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Differential D19161

[AMDGPU][llvm-mc] s_setreg* - Fix order of operands
ClosedPublic

Authored by artem.tamazov on Apr 15 2016, 7:24 AM.

Details

Reviewers
• tstellarAMD
arsenm
Commits
rGe2762423c222: [AMDGPU][llvm-mc] s_setreg* - Fix order of operands
rL266617: [AMDGPU][llvm-mc] s_setreg* - Fix order of operands
Summary

Order should match the sp3 syntax, where destination (simm16 denoting the hwreg) is coming first.

Diff Detail

Repository
rL LLVM

Event Timeline

artem.tamazov updated this revision to Diff 53881.Apr 15 2016, 7:24 AM
artem.tamazov retitled this revision from to [AMDGPU][llvm-mc] s_setreg* - Fix order of operands.
artem.tamazov updated this object.
artem.tamazov added reviewers: arsenm, • tstellarAMD.
artem.tamazov set the repository for this revision to rL LLVM.
artem.tamazov added a project: Restricted Project.
artem.tamazov added a subscriber: Restricted Project.
Herald added a subscriber: arsenm. · View Herald TranscriptApr 15 2016, 7:24 AM
• tstellarAMD accepted this revision.Apr 15 2016, 7:32 AM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Apr 15 2016, 7:32 AM
Closed by commit rL266617: [AMDGPU][llvm-mc] s_setreg* - Fix order of operands (authored by artem.tamazov). · Explain WhyApr 18 2016, 8:00 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
4 lines
test/
MC/
AMDGPU/
14 lines
Disassembler/
AMDGPU/
4 lines

Diff 54068

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

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>; >;
let mayLoad = 1 in { let mayLoad = 1 in {
defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>; defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>;
} }
defm S_SETREG_B32 : SOPK_m < defm S_SETREG_B32 : SOPK_m <
sopk<0x13, 0x12>, "s_setreg_b32", (outs), sopk<0x13, 0x12>, "s_setreg_b32", (outs),
(ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16" (ins SReg_32:$sdst, u16imm:$simm16), " $simm16, $sdst"
>; >;
// FIXME: Not on SI? // FIXME: Not on SI?
//defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>; //defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>;
defm S_SETREG_IMM32_B32 : SOPK_IMM32 < defm S_SETREG_IMM32_B32 : SOPK_IMM32 <
sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs), sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs),
(ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16" (ins i32imm:$imm, u16imm:$simm16), " $simm16, $imm"
>; >;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SOPP Instructions // SOPP Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">; def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
▲ Show 20 Lines • Show All 3,169 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AMDGPU/sopk.s

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s_cbranch_i_fork s[2:3], 0x6 s_cbranch_i_fork s[2:3], 0x6
// SICI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8] // SICI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
// VI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8] // VI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
s_getreg_b32 s2, 0x6 s_getreg_b32 s2, 0x6
// SICI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9] // SICI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9]
// VI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8] // VI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
s_setreg_b32 s2, 0x6 s_setreg_b32 0x6, s2
// SICI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb9] // SICI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x82,0xb9]
// VI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9] // VI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9]
s_setreg_imm32_b32 0xff, 0x6 s_setreg_imm32_b32 0x6, 0xff
// SICI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00] // SICI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
// VI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00] // VI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]

llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt

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0x06 0x00 0x82 0xb7 0x06 0x00 0x82 0xb7
# VI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8] # VI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
0x06 0x00 0x02 0xb8 0x06 0x00 0x02 0xb8
# VI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8] # VI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
0x06 0x00 0x82 0xb8 0x06 0x00 0x82 0xb8
# VI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9] # VI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9]
0x06 0x00 0x02 0xb9 0x06 0x00 0x02 0xb9
# VI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00] # VI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
0x06 0x00 0x00 0xba 0xff 0x00 0x00 0x00 0x06 0x00 0x00 0xba 0xff 0x00 0x00 0x00