[PPC] Enable shuffling of VSX vectors

[Carrot]

Summary

Current PPC backend enables shuffling for very limited vector types, and the default behavior for a vector with more than 2 elements is moving data through memory, it usually triggers store forwarding, it is extremely slow on power.

This simple patch explicitly enables shuffling of vectors if VSX is available. For the testcase in the bug entry, the performance is improved by 6.6x on power8. The number of instructions is reduced from 756 to 406.

[Carrot]

I forgot to mention the related bug entry is https://llvm.org/bugs/show_bug.cgi?id=27078.

[hfinkel]

lib/Target/PowerPC/PPCISelLowering.cpp

11928

I agree that this makes sense. I was going to ask that you combine this with the v2i64 logic above, and add appropriate checks for VSX data types, however, since this shouldn't have any effect on scalarized types, it is not clear that the type checks here are actually useful. Maybe just simplify this to read:

if (Subtarget.hasVSX() || Subtarget.hasQPX())
  return true;

return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);

[hfinkel]

lib/Target/PowerPC/PPCISelLowering.cpp

11928

You can remove this too:

if (VT == MVT::v2i64)
  return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves

With that, LGTM.

[Carrot]

lib/Target/PowerPC/PPCISelLowering.cpp

11928

Remove this line will cause test/CodeGen/PowerPC/vsx.ll:test80 fail. This statement uses Subtarget.hasDirectMove() to decide if shuffling is used when building a vector with 2 integers. If there is a direct move instruction (power8), the integer value can be moved to vector registers and merged. If there is no direct move instruction (power7), no shuffling is used, the integer value can only be stored to memory, and loaded to vector register.

[Eugene.Zelenko]

Committed in r268064.

lib/Target/PowerPC/PPCISelLowering.cpp

 bool
 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
                      EVT VT , unsigned DefinedValues) const {
   if (VT == MVT::v2i64)
     return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
 
-  if (Subtarget.hasQPX()) {
-    if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
-      return true;
-  }
+  if (Subtarget.hasVSX() || Subtarget.hasQPX())
+    return true;
 
   return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
 }
 
 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
   if (DisableILPPref || Subtarget.enableMachineScheduler())

test/CodeGen/PowerPC/pr27078.ll

+; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx < %s | FileCheck %s
+
+define <4 x float> @bar(float* %p, float* %q) {
+  %1 = bitcast float* %p to <12 x float>*
+  %2 = bitcast float* %q to <12 x float>*
+  %3 = load <12 x float>, <12 x float>* %1, align 16
+  %4 = load <12 x float>, <12 x float>* %2, align 16
+  %5 = fsub <12 x float> %4, %3
+  %6 = shufflevector <12 x float> %5, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
+  ret <4 x float>  %6
+
+; CHECK: vspltw
+; CHECK: vmrghw
+; CHECK: vsldoi
+}