[mips] MIPSR6 Compact jump aliases

[sdardis]

Summary

Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils.

[dsanders]

LGTM with the GPR_32 added

lib/Target/Mips/Mips32r6InstrInfo.td

820–822 ↗

(On Diff #52908)

We need GPR_32 on these so that they aren't available on MIPS64R6. 'jr' needs it too.

[sdardis]

Updated and committed as r266055.

Thanks.

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
 }
-def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6;
+def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
 
+def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
+
+def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
 //===----------------------------------------------------------------------===//
 //
 // Patterns and Pseudo Instructions
 //
 //===----------------------------------------------------------------------===//
 
 // comparisons supported via another comparison
 multiclass Cmp_Pats<ValueType VT, Instruction NOROp, Register ZEROReg> {

llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td

 //===----------------------------------------------------------------------===//
 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
 
+def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
+
+def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
 //===----------------------------------------------------------------------===//
 //
 // Patterns and Pseudo Instructions
 //
 //===----------------------------------------------------------------------===//
 
 // i64 selects
 def : MipsPat<(select i64:$cond, i64:$t, i64:$f),

llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branches.ll

 ; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32
 ; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC
 
 ; Function Attrs: nounwind
 define void @l()  {
 entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call = tail call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call1 = tail call i32 @j()
   %cmp = icmp eq i32 %call, %call1
 ; CHECK: bnec
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
 ; STATIC: nop
 ; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   tail call void @f(i32 signext -2)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc  $ra
   ret void
 }
 
 declare i32 @k()
 
 declare i32 @j()
 
 declare void @f(i32 signext) 
 
 ; Function Attrs: define void @l2()  {
 define void @l2()  {
 entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call = tail call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call1 = tail call i32 @i()
   %cmp = icmp eq i32 %call, %call1
 ; CHECK beqc
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry:
 ; STATIC: nop
 ; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   tail call void @f(i32 signext -1)
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
-; CHECK: jic $ra, 0
+; CHECK: jrc  $ra
   ret void
 }
 
 declare i32 @i()
 
 ; Function Attrs: nounwind
 define void @l3()  {
 entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call = tail call i32 @k()
   %cmp = icmp slt i32 %call, 0
 ; CHECK : bgez
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
 ; STATIC: nop
 ; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   tail call void @f(i32 signext 0)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l4()  {
 entry:
   %call = tail call i32 @k()
   %cmp = icmp slt i32 %call, 1
 ; CHECK: bgtzc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
 ; STATIC: nop
 ; STATIC: jal
   tail call void @f(i32 signext 1)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l5()  {
 entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call = tail call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %cmp = icmp sgt i32 %call, 0
 ; CHECK: blezc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
 ; STATIC: nop
 ; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   tail call void @f(i32 signext 2) 
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc  $ra
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l6()  {
 entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call = tail call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %cmp = icmp sgt i32 %call, -1
 ; CHECK: bltzc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
 ; STATIC: nop
 ; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   tail call void @f(i32 signext 3)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l7()  {
 entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call = tail call i32 @k()
   %cmp = icmp eq i32 %call, 0
 ; CHECK: bnezc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry:
 ; STATIC: nop
 ; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   tail call void @f(i32 signext 4)
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc  $ra
   ret void
 }
 
 ; Function Attrs: nounwind
 define void @l8()  {
 entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call = tail call i32 @k()
   %cmp = icmp eq i32 %call, 0
 ; CHECK: beqzc
   br i1 %cmp, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry:
 ; STATIC: nop
 ; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   tail call void @f(i32 signext 5)
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
-; CHECK: jic $ra, 0
+; CHECK: jrc  $ra
   ret void
 }
 
 define i32 @l9(i8* ()* %i) #0 {
 entry:
   %i.addr = alloca i8* ()*, align 4
   store i8* ()* %i, i8* ()** %i.addr, align 4
 ; STATIC32: jal
 ; STATIC32: nop
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %call = call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
   %cmp = icmp ne i32 %call, 0
 ; CHECK: beqzc
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   %0 = load i8* ()*, i8* ()** %i.addr, align 4
-; CHECK: jialc $25, 0
+; CHECK: jalrc $25
   %call1 = call i8* %0()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
   ret i32 -1
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll

 define i32 @call_void_void() {
 ; ALL-LABEL: call_void_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
 ; NOT-R6C:       jalr $[[TGT]]
-; R6C:           jialc $[[TGT]], 0
+; R6C:           jalrc $[[TGT]]
 
   call void @extern_void_void()
+; R6C:           jrc $ra
   ret i32 0
 }
 
 define i32 @call_i32_void() {
 ; ALL-LABEL: call_i32_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
 
 ; NOT-R6C:       jalr $[[TGT]]
-; R6C:           jialc $[[TGT]], 0
+; R6C:           jalrc $[[TGT]]
 
   %1 = call i32 @extern_i32_void()
   %2 = add i32 %1, 1
+; R6C:           jrc $ra
   ret i32 %2
 }
 
 define float @call_float_void() {
 ; ALL-LABEL: call_float_void:
 
 ; FIXME: Not sure why we don't use $gp directly on such a simple test. We should
 ;        look into it at some point.
 ; O32:           addu $[[GP:[0-9]+]], ${{[0-9]+}}, $25
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_float_void)($[[GP]])
 
 ; N64:           ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
 
 ; NOT-R6C:       jalr $[[TGT]]
-; R6C:           jialc $[[TGT]], 0
+; R6C:           jalrc $[[TGT]]
 
 
   %1 = call float @extern_float_void()
   %2 = fadd float %1, 1.0
+; R6C:           jrc $ra
   ret float %2
 }
 
 define void @musttail_call_void_void() {
 ; ALL-LABEL: musttail_call_void_void:
 
 ; O32:           lw $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
 
; ALL:           jr $[[TGT]]
   ret float %1
 }
 
 define i32 @indirect_call_void_void(void ()* %addr) {
 ; ALL-LABEL: indirect_call_void_void:
 
 ; ALL:           move $25, $4
 ; NOT-R6C:       jalr $25
-; R6C:           jialc $25, 0
-
+; R6C:           jalrc $25
 
   call void %addr()
+; R6C:           jrc $ra
   ret i32 0
 }
 
 define i32 @indirect_call_i32_void(i32 ()* %addr) {
 ; ALL-LABEL: indirect_call_i32_void:
 
 ; ALL:           move $25, $4
 ; NOT-R6C:       jalr $25
-; R6C:           jialc $25, 0
+; R6C:           jalrc $25
 
 
   %1 = call i32 %addr()
   %2 = add i32 %1, 1
+; R6C:           jrc $ra
   ret i32 %2
 }
 
 define float @indirect_call_float_void(float ()* %addr) {
 ; ALL-LABEL: indirect_call_float_void:
 
 ; ALL:           move $25, $4
 ; NOT-R6C:       jalr $25
-; R6C:           jialc $25, 0
+; R6C:           jalrc $25
 
 
   %1 = call float %addr()
   %2 = fadd float %1, 1.0
+; R6C:           jrc $ra
   ret float %2
 }
 
 ; We can't use 'musttail' here because the verifier is too conservative and
 ; prohibits any prototype difference.
 define void @tail_indirect_call_void_void(void ()* %addr) {
 ; ALL-LABEL: tail_indirect_call_void_void:
 

 ; Check that immediate addresses do not use jal.
 define i32 @jal_only_allows_symbols() {
 ; ALL-LABEL: jal_only_allows_symbols:
 
 ; ALL-NOT:       {{jal }}
 ; ALL:           addiu $[[TGT:[0-9]+]], $zero, 1234
 ; ALL-NOT:       {{jal }}
 ; NOT-R6C:       jalr $[[TGT]]
-; R6C:           jialc $[[TGT]], 0
+; R6C:           jalrc $[[TGT]]
 ; ALL-NOT:       {{jal }}
 
   call void () inttoptr (i32 1234 to void ()*)()
+; R6C:           jrc $ra
   ret i32 0
 }
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/indirectbr.ll

 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
 
 define i32 @br(i8 *%addr) {
 ; ALL-LABEL: br:
 ; NOT-R6:        jr $4 # <MCInst #{{[0-9]+}} JR
-; R6C:           jic $4, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C:           jrc $4 # <MCInst #{{[0-9]+}} JIC
 
 
 ; ALL: $BB0_1: # %L1
 ; NOT-R6:        jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6:            jr $ra # <MCInst #{{[0-9]+}} JALR
 ; R6C:           jr $ra # <MCInst #{{[0-9]+}} JALR
 ; ALL:           addiu $2, $zero, 0
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/ret.ll

 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 \
 ; RUN:     -check-prefix=R6C
 
 define void @ret_void() {
 ; ALL-LABEL: ret_void:
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
-; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C-DAG:       jrc $ra # <MCInst #{{[0-9]+}} JIC
 
   ret void
 }
 
 define i8 @ret_i8() {
 ; ALL-LABEL: ret_i8:
 ; ALL-DAG:       addiu $2, $zero, 3
 

 ; ALL-LABEL: ret_float_0x3:
 
 ; Use a constant pool
 ; O32-DAG:       lwc1 $f0, %lo($CPI
 ; N64-DAG:       lwc1 $f0, %got_ofst($CPI
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
-; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C-DAG:       jrc $ra # <MCInst #{{[0-9]+}} JIC
 
 ; float constants are written as double constants
   ret float 0x36b8000000000000
 }
 
 define double @ret_double_0x0() {
 ; ALL-LABEL: ret_double_0x0:
 
 ; NO-MTHC1-DAG:  mtc1 $zero, $f0
 ; NO-MTHC1-DAG:  mtc1 $zero, $f1
 
 ; MTHC1-DAG:     mtc1 $zero, $f0
 ; MTHC1-DAG:     mthc1 $zero, $f0
 
 ; DMTC-DAG:      dmtc1 $zero, $f0
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
-; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C-DAG:       jrc $ra # <MCInst #{{[0-9]+}} JIC
 
   ret double 0x0000000000000000
 }
 
 define double @ret_double_0x3() {
 ; ALL-LABEL: ret_double_0x3:
 
 ; Use a constant pool
 ; O32-DAG:       ldc1 $f0, %lo($CPI
 ; N64-DAG:       ldc1 $f0, %got_ofst($CPI
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
-; R6C-DAG:       jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C-DAG:       jrc $ra # <MCInst #{{[0-9]+}} JIC
 
   ret double 0x0000000000000003
 }

llvm/trunk/test/CodeGen/Mips/mips64-f128.ll

entry:
   ret fp128 %0
 }
 
 ; ALL-LABEL: load_LD_float:
 ; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gf1)
 ; ALL:   lw   $4, 0($[[R0]])
 ; ALL:   ld   $25, %call16(__extendsftf2)
 ; PRER6: jalr $25
-; R6:    jialc $25, 0
+; R6:    jalrc $25
 
 define fp128 @load_LD_float() {
 entry:
   %0 = load float, float* @gf1, align 4
   %conv = fpext float %0 to fp128
   ret fp128 %conv
 }
 
 ; ALL-LABEL: load_LD_double:
 ; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gd1)
 ; ALL:   ld   $4, 0($[[R0]])
 ; ALL:   ld   $25, %call16(__extenddftf2)
 ; PRER6: jalr $25
-; R6:    jialc $25, 0
+; R6:    jalrc $25
 
 define fp128 @load_LD_double() {
 entry:
   %0 = load double, double* @gd1, align 8
   %conv = fpext double %0 to fp128
   ret fp128 %conv
 }
 

 }
 
 ; ALL-LABEL: store_LD_float:
 ; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gld1)
 ; ALL:   ld   $4, 0($[[R0]])
 ; ALL:   ld   $5, 8($[[R0]])
 ; ALL:   ld   $25, %call16(__trunctfsf2)
 ; PRER6: jalr $25
-; R6:    jialc $25, 0
+; R6:    jalrc $25
 ; ALL:   ld   $[[R1:[0-9]+]], %got_disp(gf1)
 ; ALL:   sw   $2, 0($[[R1]])
 
 define void @store_LD_float() {
 entry:
   %0 = load fp128, fp128* @gld1, align 16
   %conv = fptrunc fp128 %0 to float
   store float %conv, float* @gf1, align 4
   ret void
 }
 
 ; ALL-LABEL: store_LD_double:
 ; ALL:   ld   $[[R0:[0-9]+]], %got_disp(gld1)
 ; ALL:   ld   $4, 0($[[R0]])
 ; ALL:   ld   $5, 8($[[R0]])
 ; ALL:   ld   $25, %call16(__trunctfdf2)
 ; PRER6: jalr $25
-; R6:    jialc $25, 0
+; R6:    jalrc $25
 ; ALL:   ld   $[[R1:[0-9]+]], %got_disp(gd1)
 ; ALL:   sd   $2, 0($[[R1]])
 
 define void @store_LD_double() {
 entry:
   %0 = load fp128, fp128* @gld1, align 16
   %conv = fptrunc fp128 %0 to double
   store double %conv, double* @gd1, align 8

 
 ; ALL-LABEL: selectCC_LD:
 ; ALL:           move $[[R0:[0-9]+]], $11
 ; ALL:           move $[[R1:[0-9]+]], $10
 ; ALL:           move $[[R2:[0-9]+]], $9
 ; ALL:           move $[[R3:[0-9]+]], $8
 ; ALL:           ld   $25, %call16(__gttf2)($gp)
 ; PRER6:         jalr $25
-; R6:            jialc $25, 0
+; R6:            jalrc $25
 
 ; C_CC_FMT:      slti $[[CC:[0-9]+]], $2, 1
 ; C_CC_FMT:      movz $[[R1]], $[[R3]], $[[CC]]
 ; C_CC_FMT:      movz $[[R0]], $[[R2]], $[[CC]]
 ; C_CC_FMT:      move $2, $[[R1]]
 ; C_CC_FMT:      move $4, $[[R0]]
 
 ; CMP_CC_FMT:    slt $[[CC:[0-9]+]], $zero, $2

llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

 0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4
 0x17 0x10 0x04 0x46 # CHECK: selnez.s $f0, $f2, $f4
 0x17 0x10 0x24 0x46 # CHECK: selnez.d $f0, $f2, $f4
 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
 0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
 0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
+0x00 0x00 0x1b 0xd8 # CHECK: jrc $27
 0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
 0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x00 0x00 0x19 0xf8 # CHECK: jalrc $25
 0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18)
 0x26 0xec 0x6f 0x7e # CHECK: sc $15, -40($19)
 0x51 0x58 0xa0 0x00 # CHECK: clo $11, $5
 0x50 0xe8 0x80 0x03 # CHECK: clz $sp, $gp
 0x40 0x00 0x00 0x00 # CHECK: ssnop
 0x0e 0x00 0x00 0x00 # CHECK: sdbbp
 0x8e 0x08 0x00 0x00 # CHECK: sdbbp 34
 0x0f 0x00 0x00 0x00 # CHECK: sync

llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

 0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4
 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
 0x00 0x64 0x10 0xc5 # CHECK: lsa $2, $3, $4, 4
 0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4
 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
 0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
 0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
 0x00 0x80 0x04 0x09 # CHECK: jr.hb $4
+0xd8 0x1b 0x00 0x00 # CHECK: jrc $27
 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0xf8 0x19 0x00 0x00 # CHECK: jalrc $25
 0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
 0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
 0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
 0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
 0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16
 0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13

llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

 0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4
 0xdd 0x10 0x64 0x00 # CHECK: dmuhu $2, $3, $4
 0x9c 0x10 0x64 0x00 # CHECK: dmul $2, $3, $4
 0x9d 0x10 0x64 0x00 # CHECK: dmulu $2, $3, $4
 0x20 0x60 0x60 0x41 # CHECK: ei
 0x20 0x60 0x6e 0x41 # CHECK: ei $14
 0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
 0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x00 0x00 0x19 0xf8 # CHECK: jalrc $25
 0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
 0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
+0x00 0x00 0x1b 0xd8 # CHECK: jrc $27
 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
 0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)
 0x48 0x3c 0x58 0xec # CHECK: ldpc $2, 123456
 0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18)
 0x37 0x38 0xe0 0x7f # CHECK: lld $zero, 112($ra)
 0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 4
 0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6)
 0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268

llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
 0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
 0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
 0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4
 0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4
 0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4
 0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4
 0x00 0x80 0x04 0x09 # CHECK: jr.hb $4
+0xd8 0x1b 0x00 0x00 # CHECK: jrc $27
 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0xf8 0x19 0x00 0x00 # CHECK: jalrc $25
 0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
 0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
 0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
 0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6
 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
 0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
 0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16

llvm/trunk/test/MC/Mips/mips32r6/valid.s

a:
                                  # CHECK:                        #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
         j       a                # CHECK: j a                    # encoding: [0b000010AA,A,A,A]
                                  # CHECK:                        #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
         j       1328             # CHECK: j 1328                 # encoding: [0x08,0x00,0x01,0x4c]
         jal       21100                # CHECK: jal 21100     # encoding: [0x0c,0x00,0x14,0x9b]
         jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
         jr      $ra              # CHECK: jr $ra                 # encoding: [0x03,0xe0,0x00,0x09]
         jr      $25              # CHECK: jr $25                 # encoding: [0x03,0x20,0x00,0x09]
+        jrc     $27              # CHECK: jrc $27                # encoding: [0xd8,0x1b,0x00,0x00]
         jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
+        jalrc   $25              # CHECK: jalrc $25              # encoding: [0xf8,0x19,0x00,0x00]
         jialc   $15, 16161       # CHECK: jialc $15, 16161       # encoding: [0xf8,0x0f,0x3f,0x21]
         jic     $12, -3920       # CHECK: jic $12, -3920         # encoding: [0xd8,0x0c,0xf0,0xb0]
         ldc2    $8, -701($at)    # CHECK: ldc2 $8, -701($1)      # encoding: [0x49,0xc8,0x0d,0x43]
         lwc2    $18,-841($a2)    # CHECK: lwc2 $18, -841($6)     # encoding: [0x49,0x52,0x34,0xb7]
         sdc2    $20,629($s2)     # CHECK: sdc2 $20, 629($18)     # encoding: [0x49,0xf4,0x92,0x75]
         swc2    $25,304($s0)     # CHECK: swc2 $25, 304($16)     # encoding: [0x49,0x79,0x81,0x30]
         ll      $v0,-153($s2)    # CHECK: ll $2, -153($18)       # encoding: [0x7e,0x42,0xb3,0xb6]
         sc      $15,-40($s3)     # CHECK: sc $15, -40($19)       # encoding: [0x7e,0x6f,0xec,0x26]

llvm/trunk/test/MC/Mips/mips64r6/valid.s

a:
                                  # CHECK:                        #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
         j       a                # CHECK: j a                    # encoding: [0b000010AA,A,A,A]
                                  # CHECK:                        #   fixup A - offset: 0, value: a, kind: fixup_Mips_26
         j       1328             # CHECK: j 1328                 # encoding: [0x08,0x00,0x01,0x4c]
         jal     21100            # CHECK: jal 21100              # encoding: [0x0c,0x00,0x14,0x9b]
         jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
         jr      $ra              # CHECK: jr $ra                 # encoding: [0x03,0xe0,0x00,0x09]
         jr      $25              # CHECK: jr $25                 # encoding: [0x03,0x20,0x00,0x09]        
+        jrc     $27              # CHECK: jrc $27                # encoding: [0xd8,0x1b,0x00,0x00]
         jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
+        jalrc   $25              # CHECK: jalrc $25              # encoding: [0xf8,0x19,0x00,0x00]
         jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
         ldc2    $8, -701($at)    # CHECK: ldc2 $8, -701($1)      # encoding: [0x49,0xc8,0x0d,0x43]
         ldpc    $2,123456        # CHECK: ldpc $2, 123456  # encoding: [0xec,0x58,0x3c,0x48]
         ll      $v0,-153($s2)    # CHECK: ll $2, -153($18)       # encoding: [0x7e,0x42,0xb3,0xb6]
         lld     $zero,112($ra)   # CHECK: lld $zero, 112($ra)    # encoding: [0x7f,0xe0,0x38,0x37]
         lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3     # encoding: [0x00,0x64,0x10,0x85]
         lwc2    $18,-841($a2)    # CHECK: lwc2 $18, -841($6)     # encoding: [0x49,0x52,0x34,0xb7]