[AMDGPU] fix readlane/readfirstlane src vgpr operand type.

[vpykhtin]

Summary

For VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand). readfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding).

For me it was a surprise why the encoding works however. This happens because SIMCCodeEmitter::getMachineOpValue always returns enum9 registry encoding and it is being cut by autogenerated encoder when written to enum8 field. For example v2 has encoding value 258 in enum9 and it becomes 2 when it is being written to a enum8 field.

[• tstellarAMD]

Does the assembler support this instruction? It would be nice to have some assembler tests that check the encoding for some edge cases.

[vpykhtin]

In D18696#389810, @tstellarAMD wrote:

Does the assembler support this instruction? It would be nice to have some assembler tests that check the encoding for some edge cases.

Yes, it has testcases:

vop1.s
// GCN: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
v_readfirstlane_b32 s1, v2

vop2.s
SICI: v_readlane_b32 s1, v2, s3 ; encoding: [0x02,0x07,0x02,0x02]
VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
v_readlane_b32 s1, v2, s3

For other usages I hope we'll submit much more testcases soon, Dmitry Preobrazhensky is working on it.

[• tstellarAMD]

LGTM.

lib/Target/AMDGPU/SIInstructions.td

 
 let Uses = [EXEC] in {
 
 // FIXME: Specify SchedRW for READFIRSTLANE_B32
 
 def V_READFIRSTLANE_B32 : VOP1 <
   0x00000002,
   (outs SReg_32:$vdst),
-  (ins VGPR_32:$src0),
+  (ins VS_32:$src0),
   "v_readfirstlane_b32 $vdst, $src0",
   []
 >;
 
 }
 
 let SchedRW = [WriteQuarterRate32] in {
 

 >;
 
 } // End isCommutable = 1
 
 defm V_READLANE_B32 : VOP2SI_3VI_m <
   vop3 <0x001, 0x289>,
   "v_readlane_b32",
   (outs SReg_32:$vdst),
-  (ins VGPR_32:$src0, SCSrc_32:$src1),
+  (ins VS_32:$src0, SCSrc_32:$src1),
   "v_readlane_b32 $vdst, $src0, $src1"
 >;
 
 defm V_WRITELANE_B32 : VOP2SI_3VI_m <
   vop3 <0x002, 0x28a>,
   "v_writelane_b32",
   (outs VGPR_32:$vdst),
   (ins SReg_32:$src0, SCSrc_32:$src1),

test/MC/Disassembler/AMDGPU/vop1_vi.txt

 # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
 
 # VI:   v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
 0x00 0x6a 0x00 0x7e
 
+# VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
+0x02 0x05 0x02 0x7e
+
 # VI:   v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x37,0x02,0x7e]
 0x02 0x37 0x02 0x7e
 
 # VI:   v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x39,0x02,0x7e]
 0x02 0x39 0x02 0x7e
 
 # VI:   v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x3b,0x02,0x7e]
 0x02 0x3b 0x02 0x7e

test/MC/Disassembler/AMDGPU/vop2_vi.txt

 # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
 
-# FIXME:   v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
-#0x01 0x00 0x89 0xd2 0x02 0x07 0x00 0x00
+# VI:   v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
+0x01 0x00 0x89 0xd2 0x02 0x07 0x00 0x00
 
 # VI:   v_writelane_b32 v1, s2, s3 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x06,0x00,0x00]
 0x01 0x00 0x8a 0xd2 0x02 0x06 0x00 0x00
 
 # VI:   v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
 0x02 0x07 0x02 0x02
 
 # VI:   v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x04]