AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStates

[• tstellarAMD]

Summary

This makes it possible to insert nops at the end of blocks.

[arsenm]

LGTM. Is this ever actually different than MI->getParent()?

[• tstellarAMD]

In D18549#385699, @arsenm wrote:

LGTM. Is this ever actually different than MI->getParent()?

MI is an iterator, so it could be BasicBlock::end(), which isn't always an instruction and doesn't have a parent.

lib/Target/AMDGPU/SIInsertWaits.cpp

if (SearchI == E) {
       return;
     }
 
     for (MachineOperand &Op : SearchI->operands()) {
       if (!Op.isReg() || !Op.isDef())
         continue;
 
       if (DPP->readsRegister(Op.getReg(), TRI)) {
-        TII->insertWaitStates(DPP, WaitStates);
+        TII->insertWaitStates(*DPP->getParent(), DPP, WaitStates);
         return;
       }
     }
   }
 }
 
 void SIInsertWaits::insertDPPWaitStates(MachineBasicBlock::iterator DPP) {
   MachineBasicBlock::reverse_iterator I(DPP);

lib/Target/AMDGPU/SIInstrInfo.h

public:
   const TargetRegisterClass *getIndirectAddrRegClass() const override;
 
   void reserveIndirectRegisters(BitVector &Reserved,
                                 const MachineFunction &MF) const;
 
   void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
               unsigned SavReg, unsigned IndexReg) const;
 
-  void insertWaitStates(MachineBasicBlock::iterator MI, int Count) const;
+  void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
+                        int Count) const;
 
   /// \brief Returns the operand named \p Op.  If \p MI does not have an
   /// operand named \c Op, this function returns nullptr.
   LLVM_READONLY
   MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
 
   LLVM_READONLY
   const MachineOperand *getNamedOperand(const MachineInstr &MI,

lib/Target/AMDGPU/SIInstrInfo.cpp

unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
   unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
   BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
           .addImm(LDSOffset)
           .addReg(TIDReg);
 
   return TmpReg;
 }
 
-void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI,
+void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB,
+                                   MachineBasicBlock::iterator MI,
                                    int Count) const {
   while (Count > 0) {
     int Arg;
     if (Count >= 8)
       Arg = 7;
     else
       Arg = Count - 1;
     Count -= 8;
-    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
+    BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
             .addImm(Arg);
   }
 }
 
 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
   MachineBasicBlock &MBB = *MI->getParent();
   DebugLoc DL = MBB.findDebugLoc(MI);
   switch (MI->getOpcode()) {

lib/Target/AMDGPU/SIRegisterInfo.cpp

case AMDGPU::SI_SPILL_S32_RESTORE: {
         }
       }
 
       // TODO: only do this when it is needed
       switch (MF->getSubtarget<AMDGPUSubtarget>().getGeneration()) {
       case AMDGPUSubtarget::SOUTHERN_ISLANDS:
         // "VALU writes SGPR" -> "SMRD reads that SGPR" needs 4 wait states
         // ("S_NOP 3") on SI
-        TII->insertWaitStates(MI, 4);
+        TII->insertWaitStates(*MBB, MI, 4);
         break;
       case AMDGPUSubtarget::SEA_ISLANDS:
         break;
       default: // VOLCANIC_ISLANDS and later
         // "VALU writes SGPR -> VMEM reads that SGPR" needs 5 wait states
         // ("S_NOP 4") on VI and later. This also applies to VALUs which write
         // VCC, but we're unlikely to see VMEM use VCC.
-        TII->insertWaitStates(MI, 5);
+        TII->insertWaitStates(*MBB, MI, 5);
       }
 
       MI->eraseFromParent();
       break;
     }
 
     // VGPR register spill
     case AMDGPU::SI_SPILL_V512_SAVE: