[SystemZ] Support llvm.frameaddress/llvm.returnaddress intrinsics

[bryanpkc]

Summary

Enable the SystemZ back-end to lower FRAMEADDR and RETURNADDR, which previously would cause the back-end to crash. Currently, only a frame count of zero is supported.

[uweigand]

This implementation of -mattr=backchain is not quite compatible to GCC's -mbackchain flag: with GCC, if a function does not need any stack frame, -mbackchain by itself does *not* force allocation of a frame, as your patch does. -mbackchain only says that *if* a frame is allocated, then the frame's back chain slot is always kept valid. In addition, GCC keeps the back chain slot valid across alloca calls and other dynamic stack allocations, which your current implementation does not. (This latter is actually a bug, not just an incompatibility.)

(Note that if a function calls __builtin_frame_address or __builtin_return_address with a nonzero frame count, then GCC does force allocation of a stack frame. This in in turn is independent of -mbackchain, however.)

Now, if we actually implement -mattr=backchain, we should do it in a way compatible with GCC, and also enable it in clang via a -mbackchain command line option. However, I'm somewhat sceptical that this is really useful. (Note that for __builtin_frame_address and __builtin_return_address to be actually safe with larger count values, all of the program needs to be built with` -mbackchain` --- but this is not the case for any system-installed libraries on any current Linux distribution ...)

[bryanpkc]

Hi Ulrich, thank you for your review. You are right that the non-zero frame traversal count is probably not very common. In the updated patch, I have removed the proposed -mattr=backchain changes. Is it better?

[uweigand]

LGTM, thanks.

lib/Target/SystemZ/SystemZFrameLowering.cpp

 }
 
 void SystemZFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                                 BitVector &SavedRegs,
                                                 RegScavenger *RS) const {
   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
 
   MachineFrameInfo *MFFrame = MF.getFrameInfo();
-  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+  const TargetSubtargetInfo &STI = MF.getSubtarget();
+  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
   bool HasFP = hasFP(MF);
   SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
   bool IsVarArg = MF.getFunction()->isVarArg();
 
   // va_start stores incoming FPR varargs in the normal way, but delegates
   // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
   // Record these pending uses, which typically include the call-saved
   // argument register R6D.
   if (IsVarArg)
     for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
       SavedRegs.set(SystemZ::ArgGPRs[I]);
 
   // If the function requires a frame pointer, record that the hard
   // frame pointer will be clobbered.
   if (HasFP)
     SavedRegs.set(SystemZ::R11D);
 
   // If the function calls other functions, record that the return
   // address register will be clobbered.
-  if (MFFrame->hasCalls())
+  const SystemZSubtarget &ZSTI = static_cast<const SystemZSubtarget &>(STI);
+  if (MFFrame->hasCalls() || ZSTI.hasBackChain())
     SavedRegs.set(SystemZ::R14D);
 
   // If we are saving GPRs other than the stack pointer, we might as well
   // save and restore the stack pointer at the same time, via STMG and LMG.
   // This allows the deallocation to be done by the LMG, rather than needing
   // a separate %r15 addition.
   const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
   for (unsigned I = 0; CSRegs[I]; ++I) {
for (auto &Save : CSI) {
         unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
             nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
         BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
             .addCFIIndex(CFIIndex);
       }
     }
   }
 
+  const TargetSubtargetInfo &STI = MF.getSubtarget();
+  const SystemZSubtarget &ZSTI = static_cast<const SystemZSubtarget &>(STI);
   uint64_t StackSize = getAllocatedStackSize(MF);
+
+  // If back chains are used, copy the old stack pointer to R14.
+  if (ZSTI.hasBackChain()) {
+    assert(StackSize && "Must allocate stack frame to svae back chain");
+    BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R14D)
+      .addReg(SystemZ::R15D);
+  }
+
   if (StackSize) {
     // Allocate StackSize bytes.
     int64_t Delta = -int64_t(StackSize);
     emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
 
     // Add CFI for the allocation.
     unsigned CFIIndex = MMI.addFrameInst(
         MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
if (HasFP) {
 
     // Mark the FramePtr as live at the beginning of every block except
     // the entry block.  (We'll have marked R11 as live on entry when
     // saving the GPRs.)
     for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
       I->addLiveIn(SystemZ::R11D);
   }
 
+  // Now store the old stack pointer to the back chain slot, if used.
+  if (ZSTI.hasBackChain()) {
+    const TargetRegisterInfo *TRI = STI.getRegisterInfo();
+    const TargetInstrInfo *TII = STI.getInstrInfo();
+    int BackChainIdx = MFFrame->CreateFixedObject(8,
+        -(SystemZMC::CallFrameSize + StackSize), false);
+    // int BackChainIdx = ZFI->getFramePointerSaveIndex();
+    TII->storeRegToStackSlot(MBB, MBBI, SystemZ::R14D, true, BackChainIdx,
+                             &SystemZ::GR64BitRegClass, TRI);
+  }
+
   // Skip over the FPR saves.
   SmallVector<unsigned, 8> CFIIndexes;
   for (auto &Save : CSI) {
     unsigned Reg = Save.getReg();
     if (SystemZ::FP64BitRegClass.contains(Reg)) {
       if (MBBI != MBB.end() &&
           (MBBI->getOpcode() == SystemZ::STD ||
            MBBI->getOpcode() == SystemZ::STDY))
int SystemZFrameLowering::getFrameIndexReference(const MachineFunction &MF,
   Offset += getAllocatedStackSize(MF);
 
   return Offset;
 }
 
 uint64_t SystemZFrameLowering::
 getAllocatedStackSize(const MachineFunction &MF) const {
   const MachineFrameInfo *MFFrame = MF.getFrameInfo();
+  const TargetSubtargetInfo &STI = MF.getSubtarget();
+  const SystemZSubtarget &ZSTI = static_cast<const SystemZSubtarget &>(STI);
 
   // Start with the size of the local variables and spill slots.
   uint64_t StackSize = MFFrame->getStackSize();
 
   // We need to allocate the ABI-defined 160-byte base area whenever
   // we allocate stack space for our own use and whenever we call another
-  // function.
-  if (StackSize || MFFrame->hasVarSizedObjects() || MFFrame->hasCalls())
+  // function, or if back chain support has been requested.
+  if (StackSize || MFFrame->hasVarSizedObjects() || MFFrame->hasCalls() ||
+      ZSTI.hasBackChain())
     StackSize += SystemZMC::CallFrameSize;
 
   return StackSize;
 }
 
 bool
 SystemZFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
   // The ABI requires us to allocate 160 bytes of stack space for the callee,

lib/Target/SystemZ/SystemZISelLowering.h

SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
                             SelectionDAG &DAG, unsigned Opcode,
                             SDValue GOTOffset) const;
   SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
                                 SelectionDAG &DAG) const;
   SDValue lowerBlockAddress(BlockAddressSDNode *Node,
                             SelectionDAG &DAG) const;
   SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
   SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
+  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;

lib/Target/SystemZ/SystemZISelLowering.cpp

SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
   else
     Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
                                        CP->getAlignment(), CP->getOffset());
 
   // Use LARL to load the address of the constant pool entry.
   return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
 }
 
+SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
+                                              SelectionDAG &DAG) const {
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  MFI->setFrameAddressIsTaken(true);
+
+  SDLoc DL(Op);
+  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  EVT PtrVT = getPointerTy(DAG.getDataLayout());
+
+  // If the back chain frame index has not been allocated yet, do so.
+  SystemZMachineFunctionInfo *FI = MF.getInfo<SystemZMachineFunctionInfo>();
+  int BackChainIdx = FI->getFramePointerSaveIndex();
+  if (!BackChainIdx) {
+    // By definition, the frame address is the address of the back chain.
+    BackChainIdx = MFI->CreateFixedObject(8, -SystemZMC::CallFrameSize, false);
+    FI->setFramePointerSaveIndex(BackChainIdx);
+  }
+  SDValue BackChain = DAG.getFrameIndex(BackChainIdx, PtrVT);
+
+  // FIXME The frontend should detect this case.
+  if (Depth > 0 && !Subtarget.hasBackChain()) {
+    report_fatal_error("Cannot traverse call stack without -mattr=backchain.");
+  }
+
+  while (Depth--)
+    BackChain = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
+                            BackChain, MachinePointerInfo(),
+                            false, false, false, 0);
+
+  return BackChain;
+}
+
+SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
+                                               SelectionDAG &DAG) const {
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  MFI->setReturnAddressIsTaken(true);
+
+  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
+    return SDValue();
+
+  SDLoc DL(Op);
+  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  EVT PtrVT = getPointerTy(DAG.getDataLayout());
+
+  if (Depth > 0) {
+    const SystemZFrameLowering *TFI = Subtarget.getFrameLowering();
+    SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);
+    SDValue Offset = DAG.getConstant(TFI->getRegSpillOffset(SystemZ::R14D),
+                                     DL, PtrVT);
+    return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
+                       DAG.getNode(ISD::ADD, DL, PtrVT, FrameAddr, Offset),
+                       MachinePointerInfo(), false, false, false, 0);
+  }
+
+  if (Subtarget.hasBackChain()) {
+    // If the return address frame index has not been allocated yet, do so.
+    SystemZMachineFunctionInfo *FI = MF.getInfo<SystemZMachineFunctionInfo>();
+    int RetAddrIdx = FI->getReturnAddrSaveIndex();
+    if (!RetAddrIdx) {
+      const SystemZFrameLowering *TFI = Subtarget.getFrameLowering();
+      int R14Offset =
+        TFI->getRegSpillOffset(SystemZ::R14D) - SystemZMC::CallFrameSize;
+      RetAddrIdx = MFI->CreateFixedObject(8, R14Offset, false);
+      FI->setReturnAddrSaveIndex(RetAddrIdx);
+    }
+    SDValue RetAddrSlot = DAG.getFrameIndex(RetAddrIdx, PtrVT);
+    return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), RetAddrSlot,
+                       MachinePointerInfo(), false, false, false, 0);
+  } else {
+    // Return R14D, which has the return address. Mark it an implicit live-in.
+    unsigned LinkReg = MF.addLiveIn(SystemZ::R14D, &SystemZ::GR64BitRegClass);
+    return DAG.getCopyFromReg(DAG.getEntryNode(), DL, LinkReg, PtrVT);
+  }
+}
+
 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
                                             SelectionDAG &DAG) const {
   SDLoc DL(Op);
   SDValue In = Op.getOperand(0);
   EVT InVT = In.getValueType();
   EVT ResVT = Op.getValueType();
 
   // Convert loads directly.  This is normally done by DAGCombiner,
SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
 
   // Otherwise just treat the current form as legal.
   return Op;
 }
 
 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
                                               SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
+  case ISD::FRAMEADDR:
+    return lowerFRAMEADDR(Op, DAG);
+  case ISD::RETURNADDR:
+    return lowerRETURNADDR(Op, DAG);
   case ISD::BR_CC:
     return lowerBR_CC(Op, DAG);
   case ISD::SELECT_CC:
     return lowerSELECT_CC(Op, DAG);
   case ISD::SETCC:
     return lowerSETCC(Op, DAG);
   case ISD::GlobalAddress:
     return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);

lib/Target/SystemZ/SystemZMachineFunctionInfo.h

 class SystemZMachineFunctionInfo : public MachineFunctionInfo {
   virtual void anchor();
   unsigned LowSavedGPR;
   unsigned HighSavedGPR;
   unsigned VarArgsFirstGPR;
   unsigned VarArgsFirstFPR;
   unsigned VarArgsFrameIndex;
   unsigned RegSaveFrameIndex;
+  int FramePointerSaveIndex;
+  int ReturnAddrSaveIndex; 
   bool ManipulatesSP;
   unsigned NumLocalDynamics;
 
 public:
   explicit SystemZMachineFunctionInfo(MachineFunction &MF)
     : LowSavedGPR(0), HighSavedGPR(0), VarArgsFirstGPR(0), VarArgsFirstFPR(0),
-      VarArgsFrameIndex(0), RegSaveFrameIndex(0), ManipulatesSP(false),
-      NumLocalDynamics(0) {}
+      VarArgsFrameIndex(0), RegSaveFrameIndex(0),
+      FramePointerSaveIndex(0), ReturnAddrSaveIndex(0),
+      ManipulatesSP(false), NumLocalDynamics(0) {}
 
   // Get and set the first call-saved GPR that should be saved and restored
   // by this function.  This is 0 if no GPRs need to be saved or restored.
   unsigned getLowSavedGPR() const { return LowSavedGPR; }
   void setLowSavedGPR(unsigned Reg) { LowSavedGPR = Reg; }
 
   // Get and set the last call-saved GPR that should be saved and restored
   // by this function.
public:
   unsigned getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
   void setVarArgsFrameIndex(unsigned FI) { VarArgsFrameIndex = FI; }
 
   // Get and set the frame index of the register save area
   // (i.e. the incoming stack pointer).
   unsigned getRegSaveFrameIndex() const { return RegSaveFrameIndex; }
   void setRegSaveFrameIndex(unsigned FI) { RegSaveFrameIndex = FI; }
 
+  // Get and set the frame index of where the old frame pointer is stored.
+  int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
+  void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
+
+  // Get and set the frame index of where the return address is stored.
+  int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; }
+  void setReturnAddrSaveIndex(int Idx) { ReturnAddrSaveIndex = Idx; }
+
   // Get and set whether the function directly manipulates the stack pointer,
   // e.g. through STACKSAVE or STACKRESTORE.
   bool getManipulatesSP() const { return ManipulatesSP; }
   void setManipulatesSP(bool MSP) { ManipulatesSP = MSP; }
 
   // Count number of local-dynamic TLS symbols used.
   unsigned getNumLocalDynamicTLSAccesses() const { return NumLocalDynamics; }
   void incNumLocalDynamicTLSAccesses() { ++NumLocalDynamics; }
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/SystemZ/SystemZProcessors.td

 >;
 
 def FeatureVector : SystemZFeature<
   "vector", "Vector",
   "Assume that the vectory facility is installed"
 >;
 def FeatureNoVector : SystemZMissingFeature<"Vector">;
 
+def FeatureBackChain : SystemZFeature<
+  "backchain", "BackChain",
+  "Enable the saving of back chains in call frames"
+>;
+
 def : Processor<"generic", NoItineraries, []>;
 def : Processor<"z10", NoItineraries, []>;
 def : Processor<"z196", NoItineraries,
                 [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
                  FeatureFPExtension, FeaturePopulationCount,
                  FeatureFastSerialization, FeatureInterlockedAccess1]>;
 def : Processor<"zEC12", NoItineraries,
                 [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,

lib/Target/SystemZ/SystemZSubtarget.h

protected:
   bool HasFPExtension;
   bool HasPopulationCount;
   bool HasFastSerialization;
   bool HasInterlockedAccess1;
   bool HasMiscellaneousExtensions;
   bool HasTransactionalExecution;
   bool HasProcessorAssist;
   bool HasVector;
+  bool HasBackChain;
 
 private:
   Triple TargetTriple;
   SystemZInstrInfo InstrInfo;
   SystemZTargetLowering TLInfo;
   SystemZSelectionDAGInfo TSInfo;
   SystemZFrameLowering FrameLowering;
 
   SystemZSubtarget &initializeSubtargetDependencies(StringRef CPU,
                                                     StringRef FS);
 public:
   SystemZSubtarget(const Triple &TT, const std::string &CPU,
                    const std::string &FS, const TargetMachine &TM);
 
-  const TargetFrameLowering *getFrameLowering() const override {
+  const SystemZFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
   const SystemZInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const SystemZRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
   const SystemZTargetLowering *getTargetLowering() const override {
     return &TLInfo;
public:
   bool hasTransactionalExecution() const { return HasTransactionalExecution; }
 
   // Return true if the target has the processor-assist facility.
   bool hasProcessorAssist() const { return HasProcessorAssist; }
 
   // Return true if the target has the vector facility.
   bool hasVector() const { return HasVector; }
 
+  // Return true if the back chain needs to be saved.
+  bool hasBackChain() const { return HasBackChain; }
+
   // Return true if GV can be accessed using LARL for reloc model RM
   // and code model CM.
   bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
                        CodeModel::Model CM) const;
 
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 };
 } // end namespace llvm
 
 #endif

lib/Target/SystemZ/SystemZSubtarget.cpp

 SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
                                    const TargetMachine &TM)
     : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasPopulationCount(false), HasFastSerialization(false),
       HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
       HasTransactionalExecution(false), HasProcessorAssist(false),
-      HasVector(false), TargetTriple(TT),
+      HasVector(false), HasBackChain(false), TargetTriple(TT),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       TSInfo(), FrameLowering() {}
 
 // Return true if GV binds locally under reloc model RM.
 static bool bindsLocally(const GlobalValue *GV, Reloc::Model RM) {
   // For non-PIC, all symbols bind locally.
   if (RM == Reloc::Static)
     return true;

test/CodeGen/SystemZ/frameaddr-01.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Return the current function's frame address by taking the address
+; of the optional back chain slot.
+define i8* @fp0() nounwind {
+entry:
+; CHECK-LABEL: fp0:
+; CHECK: la   %r2, 0(%r15)
+; CHECK: br   %r14
+  %0 = tail call i8* @llvm.frameaddress(i32 0)
+  ret i8* %0
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone

test/CodeGen/SystemZ/frameaddr-02.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=backchain | FileCheck %s
+
+; With back chain support, the frame address is always preserved at 0(%r15).
+define i8* @fp2b() nounwind {
+entry:
+; CHECK-LABEL: fp2b:
+; CHECK: stmg %r14, %r15, 112(%r15)
+; CHECK: lgr  %r14, %r15
+; CHECK: aghi %r15, -160
+; CHECK: stg  %r14, 0(%r15)
+; CHECK: lg   %r1, 160(%r15)
+; CHECK: lg   %r2, 0(%r1)
+; CHECK: lmg  %r14, %r15, 272(%r15)
+; CHECK: br   %r14
+  %0 = tail call i8* @llvm.frameaddress(i32 2)
+  ret i8* %0
+}
+
+define i8* @fp1bfp() nounwind "no-frame-pointer-elim"="true" {
+entry:
+; CHECK-LABEL: fp1bfp:
+; CHECK: stmg %r11, %r15, 88(%r15)
+; CHECK: lgr  %r14, %r15
+; CHECK: aghi %r15, -160
+; CHECK: lgr  %r11, %r15
+; CHECK: stg  %r14, 0(%r11)
+; CHECK: lg   %r2, 160(%r11)
+; CHECK: lmg  %r11, %r15, 248(%r11)
+; CHECK: br   %r14
+  %0 = tail call i8* @llvm.frameaddress(i32 1)
+  ret i8* %0
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone

test/CodeGen/SystemZ/ret-addr-01.ll

+; Test support for the llvm.returnaddress intrinsic.
+; 
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Without back chain support, just return the current function's
+; return address from link register.
+define i8* @rt0() norecurse nounwind readnone {
+entry:
+; CHECK-LABEL: rt0:
+; CHECK: lgr  %r2, %r14
+; CHECK: br   %r14
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone

test/CodeGen/SystemZ/ret-addr-02.ll

+; Test support for the llvm.returnaddress intrinsic.
+; 
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=backchain | FileCheck %s
+
+; With back chain support, the return address is always preserved.
+define i8* @rt0() norecurse nounwind readnone {
+entry:
+; CHECK-LABEL: rt0:
+; CHECK: stmg %r14, %r15, 112(%r15)
+; CHECK: lgr  %r14, %r15
+; CHECK: aghi %r15, -160
+; CHECK: stg  %r14, 0(%r15)
+; CHECK: lg   %r2, 272(%r15)
+; CHECK: lmg  %r14, %r15, 272(%r15)
+; CHECK: br   %r14
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+define i8* @rt2b() nounwind readnone {
+entry:
+; CHECK-LABEL: rt2b:
+; CHECK: stmg %r14, %r15, 112(%r15)
+; CHECK: lgr  %r14, %r15
+; CHECK: aghi %r15, -160
+; CHECK: stg  %r14, 0(%r15)
+; CHECK: lg   %r1, 160(%r15)
+; CHECK: lg   %r1, 0(%r1)
+; CHECK: lg   %r2, 112(%r1)
+; CHECK: lmg  %r14, %r15, 272(%r15)
+; CHECK: br   %r14
+  %0 = tail call i8* @llvm.returnaddress(i32 2)
+  ret i8* %0
+}
+
+define i8* @rt1bfp() nounwind "no-frame-pointer-elim"="true" readnone {
+entry:
+; CHECK-LABEL: rt1bfp:
+; CHECK: stmg %r11, %r15, 88(%r15)
+; CHECK: lgr  %r14, %r15
+; CHECK: aghi %r15, -160
+; CHECK: lgr  %r11, %r15
+; CHECK: stg  %r14, 0(%r11)
+; CHECK: lg   %r1, 160(%r11)
+; CHECK: lg   %r2, 112(%r1)
+; CHECK: lmg  %r11, %r15, 248(%r11)
+; CHECK: br %r14
+  %0 = tail call i8* @llvm.returnaddress(i32 1)
+  ret i8* %0
+}
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone