[AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3

[• tstellarAMD]

LGTM.

[SamWot]

Removed unnecessary comment

[SamWot]

Submitted r263789

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

else {
       assert(isExpr());
       Inst.addOperand(MCOperand::createExpr(Expr));
     }
   }
 
   bool defaultTokenHasSuffix() const {
     StringRef Token(Tok.Data, Tok.Length);
 
-    return Token.endswith("_e32") || Token.endswith("_e64") || 
+    return Token.endswith("_e32") || Token.endswith("_e64") ||
       Token.endswith("_dpp");
   }
 
   bool isToken() const override {
     return Kind == Token;
   }
 
   bool isImm() const override {
     return Kind == Immediate;
   }
 
   bool isInlinableImm() const {
     if (!isImm() || Imm.Type != AMDGPUOperand::ImmTyNone /* Only plain
       immediates are inlinable (e.g. "clamp" attribute is not) */ )
       return false;
     // TODO: We should avoid using host float here. It would be better to
-    // check the float bit values which is what a few other places do. 
+    // check the float bit values which is what a few other places do.
     // We've had bot failures before due to weird NaN support on mips hosts.
     const float F = BitsToFloat(Imm.Val);
     // TODO: Add 1/(2*pi) for VI
     return (Imm.Val <= 64 && Imm.Val >= -16) ||
            (F == 0.0 || F == 0.5 || F == -0.5 || F == 1.0 || F == -1.0 ||
            F == 2.0 || F == -2.0 || F == 4.0 || F == -4.0);
   }
 
public:
 
   bool isRowMask() const {
     return isImmTy(ImmTyDppRowMask);
   }
 
   bool isBoundCtrl() const {
     return isImmTy(ImmTyDppBoundCtrl);
   }
-  
   void setModifiers(unsigned Mods) {
     assert(isReg() || (isImm() && Imm.Modifiers == 0));
     if (isReg())
       Reg.Modifiers = Mods;
     else
       Imm.Modifiers = Mods;
   }
 
bool isVCSrc64() const {
     return isInlinableImm() || isRegClass(AMDGPU::VS_64RegClassID);
   }
 
   bool isVSrc32() const {
     return isImm() || isVCSrc32();
   }
 
   bool isVSrc64() const {
-    // TODO: Check if the 64-bit value (coming from assembly source) can be 
+    // TODO: Check if the 64-bit value (coming from assembly source) can be
     // narrowed to 32 bits (in the instruction stream). That require knowledge
     // of instruction type (unsigned/signed, floating or "untyped"/B64),
     // see [AMD GCN3 ISA 6.3.1].
     // TODO: How 64-bit values are formed from 32-bit literals in _B64 insns?
     return isImm() || isVCSrc64();
   }
 
   bool isMem() const override {
public:
   void print(raw_ostream &OS) const override {
     switch (Kind) {
     case Register:
       OS << "<register " << getReg() << " mods: " << Reg.Modifiers << '>';
       break;
     case Immediate:
       if (Imm.Type != AMDGPUOperand::ImmTyNone)
         OS << getImm();
-      else 
+      else
         OS << '<' << getImm() << " mods: " << Imm.Modifiers << '>';
       break;
     case Token:
       OS << '\'' << getToken() << '\'';
       break;
     case Expression:
       OS << "<expr " << *Expr << '>';
       break;
AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
   }
 
   Operands.push_back(AMDGPUOperand::CreateImm(Bit, S, ImmTy));
   return MatchOperand_Success;
 }
 
 typedef std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalImmIndexMap;
 
-void addOptionalImmOperand(MCInst& Inst, const OperandVector& Operands, 
-                           OptionalImmIndexMap& OptionalIdx, 
+void addOptionalImmOperand(MCInst& Inst, const OperandVector& Operands,
+                           OptionalImmIndexMap& OptionalIdx,
                            enum AMDGPUOperand::ImmTy ImmT, int64_t Default = 0) {
   auto i = OptionalIdx.find(ImmT);
   if (i != OptionalIdx.end()) {
     unsigned Idx = i->second;
     ((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);
   } else {
     Inst.addOperand(MCOperand::createImm(Default));
   }
return ((Imm >= 0x000) && (Imm <= 0x0ff)) ||
            (Imm == 0x140) ||
            (Imm == 0x141) ||
            (Imm == 0x142) ||
            (Imm == 0x143);
   }
   return false;
 }
 
-AMDGPUAsmParser::OperandMatchResultTy 
+AMDGPUAsmParser::OperandMatchResultTy
 AMDGPUAsmParser::parseDPPCtrlOps(OperandVector &Operands) {
   // ToDo: use same syntax as sp3 for dpp_ctrl
   SMLoc S = Parser.getTok().getLoc();
   StringRef Prefix;
   int64_t Int;
-  
-  switch(getLexer().getKind()) {
-    default: return MatchOperand_NoMatch;
-    case AsmToken::Identifier: {
-      Prefix = Parser.getTok().getString();
+  if (getLexer().getKind() == AsmToken::Identifier) {
+  } else {
+    return MatchOperand_NoMatch;
+  }
 
-      Parser.Lex();
-      if (getLexer().isNot(AsmToken::Colon))
-        return MatchOperand_ParseFail;
+  if (Prefix == "row_mirror") {
+    Int = 0x140;
+  } else if (Prefix == "row_half_mirror") {
+    Int = 0x141;
+  } else {
 
+    if (Prefix == "quad_perm") {
+      // quad_perm:[%d,%d,%d,%d]
+      Parser.Lex();
+      if (getLexer().isNot(AsmToken::LBrac))
+        return MatchOperand_ParseFail;
+
       Parser.Lex();
       if (getLexer().isNot(AsmToken::Integer))
         return MatchOperand_ParseFail;
+      Int = getLexer().getTok().getIntVal();
 
-      if (getParser().parseAbsoluteExpression(Int))
+      Parser.Lex();
+      if (getLexer().isNot(AsmToken::Comma))
         return MatchOperand_ParseFail;
-      break;
-    }
-  }
+      Parser.Lex();
+      if (getLexer().isNot(AsmToken::Integer))
+        return MatchOperand_ParseFail;
+      Int += (getLexer().getTok().getIntVal() << 2);
 
-  if (Prefix.equals("row_shl")) {
+      Parser.Lex();
+      if (getLexer().isNot(AsmToken::Comma))
+        return MatchOperand_ParseFail;
+      Parser.Lex();
+      if (getLexer().isNot(AsmToken::Integer))
+        return MatchOperand_ParseFail;
+      Int += (getLexer().getTok().getIntVal() << 4);
+
+      Parser.Lex();
+      if (getLexer().isNot(AsmToken::Comma))
+        return MatchOperand_ParseFail;
+      Parser.Lex();
+      if (getLexer().isNot(AsmToken::Integer))
+        return MatchOperand_ParseFail;
+      Int += (getLexer().getTok().getIntVal() << 6);
+
+      Parser.Lex();
+      if (getLexer().isNot(AsmToken::RBrac))
+        return MatchOperand_ParseFail;
+
+    } else {
+      // sel:%d
+      Parser.Lex();
+      if (getLexer().isNot(AsmToken::Integer))
+        return MatchOperand_ParseFail;
+      Int = getLexer().getTok().getIntVal();
+
+      if (Prefix == "row_shl") {
         Int |= 0x100;
-  } else if (Prefix.equals("row_shr")) {
+      } else if (Prefix == "row_shr") {
         Int |= 0x110;
-  } else if (Prefix.equals("row_ror")) {
+      } else if (Prefix == "row_ror") {
         Int |= 0x120;
-  } else if (Prefix.equals("wave_shl")) {
+      } else if (Prefix == "wave_shl") {
         Int = 0x130;
-  } else if (Prefix.equals("wave_rol")) {
+      } else if (Prefix == "wave_rol") {
         Int = 0x134;
-  } else if (Prefix.equals("wave_shr")) {
+      } else if (Prefix == "wave_shr") {
         Int = 0x138;
-  } else if (Prefix.equals("wave_ror")) {
+      } else if (Prefix == "wave_ror") {
         Int = 0x13C;
-  } else if (Prefix.equals("row_mirror")) {
-    Int = 0x140;
-  } else if (Prefix.equals("row_half_mirror")) {
-    Int = 0x141;
-  } else if (Prefix.equals("row_bcast")) {
+      } else if (Prefix == "row_bcast") {
         if (Int == 15) {
           Int = 0x142;
         } else if (Int == 31) {
           Int = 0x143;
         }
-  } else if (!Prefix.equals("quad_perm")) {
+      } else {
         return MatchOperand_NoMatch;
       }
-  Operands.push_back(AMDGPUOperand::CreateImm(Int, S, 
+    }
+  }
+  Parser.Lex(); // eat last token
+
+  Operands.push_back(AMDGPUOperand::CreateImm(Int, S,
                                               AMDGPUOperand::ImmTyDppCtrl));
   return MatchOperand_Success;
 }
 
 static const OptionalOperand DPPOptionalOps [] = {
   {"row_mask", AMDGPUOperand::ImmTyDppRowMask, false, 0xf, nullptr},
   {"bank_mask", AMDGPUOperand::ImmTyDppBankMask, false, 0xf, nullptr},
   {"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, -1, nullptr}
 };
 
-AMDGPUAsmParser::OperandMatchResultTy 
+AMDGPUAsmParser::OperandMatchResultTy
 AMDGPUAsmParser::parseDPPOptionalOps(OperandVector &Operands) {
   SMLoc S = Parser.getTok().getLoc();
   OperandMatchResultTy Res = parseOptionalOps(DPPOptionalOps, Operands);
   // XXX - sp3 use syntax "bound_ctrl:0" to indicate that bound_ctrl bit was set
   if (Res == MatchOperand_Success) {
     AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands.back());
     // If last operand was parsed as bound_ctrl we should replace it with correct value (1)
     if (Op.isImmTy(AMDGPUOperand::ImmTyDppBoundCtrl)) {

 void AMDGPUAsmParser::cvtDPP_mod(MCInst &Inst, const OperandVector &Operands) {
   cvtDPP(Inst, Operands, true);
 }
 
 void AMDGPUAsmParser::cvtDPP_nomod(MCInst &Inst, const OperandVector &Operands) {
   cvtDPP(Inst, Operands, false);
 }
 
-void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, 
+void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands,
                              bool HasMods) {
   OptionalImmIndexMap OptionalIdx;
 
   unsigned I = 1;
   const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
   for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
     ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
   }

lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

if (InputModifiers & SISrcMods::ABS)
     O << '|';
 }
 
 
 void AMDGPUInstPrinter::printDPPCtrlOperand(const MCInst *MI, unsigned OpNo,
                                              raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   if (Imm <= 0x0ff) {
-    O << " quad_perm:";
-    printU8ImmDecOperand(MI, OpNo, O);
+    O << " quad_perm:[";
+    O << formatDec(Imm & 0x3)         << ",";
+    O << formatDec((Imm & 0xc)  >> 2) << ",";
+    O << formatDec((Imm & 0x30) >> 4) << ",";
+    O << formatDec((Imm & 0xc0) >> 6) << "]";
   } else if ((Imm >= 0x101) && (Imm <= 0x10f)) {
     O << " row_shl:";
     printU4ImmDecOperand(MI, OpNo, O);
   } else if ((Imm >= 0x111) && (Imm <= 0x11f)) {
     O << " row_shr:";
     printU4ImmDecOperand(MI, OpNo, O);
   } else if ((Imm >= 0x121) && (Imm <= 0x12f)) {
     O << " row_ror:";
     printU4ImmDecOperand(MI, OpNo, O);
   } else if (Imm == 0x130) {
     O << " wave_shl:1";
   } else if (Imm == 0x134) {
     O << " wave_rol:1";
   } else if (Imm == 0x138) {
     O << " wave_shr:1";
   } else if (Imm == 0x13c) {
     O << " wave_ror:1";
   } else if (Imm == 0x140) {
-    O << " row_mirror:1";
+    O << " row_mirror";
   } else if (Imm == 0x141) {
-    O << " row_half_mirror:1";
+    O << " row_half_mirror";
   } else if (Imm == 0x142) {
     O << " row_bcast:15";
   } else if (Imm == 0x143) {
     O << " row_bcast:31";
   } else {
     llvm_unreachable("Invalid dpp_ctrl value");
   }
 }

test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll

 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
 
 ; FIXME: The register allocator / scheduler should be able to avoid these hazards.
 
 ; VI-LABEL: {{^}}dpp_test:
 ; VI: v_mov_b32_e32 v0, s{{[0-9]+}}
 ; VI: s_nop 1
-; VI: v_mov_b32_dpp v0, v0 quad_perm:1 row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
+; VI: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
 define void @dpp_test(i32 addrspace(1)* %out, i32 %in) {
   %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 
 ; VI-LABEL: {{^}}dpp_wait_states:
 ; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}
 ; VI: s_nop 1
-; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:1 row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
 ; VI: s_nop 1
-; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:1 row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
 define void @dpp_wait_states(i32 addrspace(1)* %out, i32 %in) {
   %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0
   %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0
   store i32 %tmp1, i32 addrspace(1)* %out
   ret void
 }
 
 ; VI-LABEL: {{^}}dpp_first_in_bb:
 ; VI: s_nop 1
-; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:1 row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
 ; VI: s_nop 1
-; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:1 row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
 ; VI: s_nop 1
-; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:1 row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
 define void @dpp_first_in_bb(float addrspace(1)* %out, float addrspace(1)* %in, float %cond, float %a, float %b) {
   %cmp = fcmp oeq float %cond, 0.0
   br i1 %cmp, label %if, label %else
 
 if:
   %out_val = load float, float addrspace(1)* %out
   %if_val = fadd float %a, %out_val
   br label %endif

test/MC/AMDGPU/vop_dpp.s

 // RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
 // RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
 
 //===----------------------------------------------------------------------===//
 // Check dpp_ctrl values
 //===----------------------------------------------------------------------===//
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 quad_perm:37 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x25,0x00,0xff]
-v_mov_b32 v0, v0 quad_perm:37
+// VI: v_mov_b32_dpp v0, v0 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x58,0x00,0xff]
+v_mov_b32 v0, v0 quad_perm:[0,2,1,1]
 
 // NOSICI: error:
 // VI: v_mov_b32_dpp v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x01,0xff]
 v_mov_b32 v0, v0 row_shl:1
 
 // NOSICI: error:
 // VI: v_mov_b32_dpp v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x1f,0x01,0xff]
 v_mov_b32 v0, v0 row_shr:0xf

 // VI: v_mov_b32_dpp v0, v0 wave_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x38,0x01,0xff]
 v_mov_b32 v0, v0 wave_shr:1
 
 // NOSICI: error:
 // VI: v_mov_b32_dpp v0, v0 wave_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x3c,0x01,0xff]
 v_mov_b32 v0, v0 wave_ror:1
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 row_mirror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x40,0x01,0xff]
-v_mov_b32 v0, v0 row_mirror:1
+// VI: v_mov_b32_dpp v0, v0 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x40,0x01,0xff]
+v_mov_b32 v0, v0 row_mirror
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 row_half_mirror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x41,0x01,0xff]
-v_mov_b32 v0, v0 row_half_mirror:1
+// VI: v_mov_b32_dpp v0, v0 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x41,0x01,0xff]
+v_mov_b32 v0, v0 row_half_mirror
 
 // NOSICI: error:
 // VI: v_mov_b32_dpp v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x42,0x01,0xff]
 v_mov_b32 v0, v0 row_bcast:15
 
 // NOSICI: error:
 // VI: v_mov_b32_dpp v0, v0 row_bcast:31 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x43,0x01,0xff]
 v_mov_b32 v0, v0 row_bcast:31
 
 //===----------------------------------------------------------------------===//
 // Check optional fields
 //===----------------------------------------------------------------------===//
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 quad_perm:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0xa1]
-v_mov_b32 v0, v0 quad_perm:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
+// VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 quad_perm:1 row_mask:0xa bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x00,0xaf]
-v_mov_b32 v0, v0 quad_perm:1 row_mask:0xa
+// VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xaf]
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 quad_perm:1 row_mask:0xf bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x00,0xf1]
-v_mov_b32 v0, v0 quad_perm:1 bank_mask:0x1
+// VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xf1]
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] bank_mask:0x1
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 quad_perm:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0xff]
-v_mov_b32 v0, v0 quad_perm:1 bound_ctrl:0
+// VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xff]
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] bound_ctrl:0
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 quad_perm:1 row_mask:0xa bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x00,0xa1]
-v_mov_b32 v0, v0 quad_perm:1 row_mask:0xa bank_mask:0x1
+// VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xa1]
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 quad_perm:1 row_mask:0xa bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0xaf]
-v_mov_b32 v0, v0 quad_perm:1 row_mask:0xa bound_ctrl:0
+// VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xaf]
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bound_ctrl:0
 
 // NOSICI: error:
-// VI: v_mov_b32_dpp v0, v0 quad_perm:1 row_mask:0xf bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0xf1]
-v_mov_b32 v0, v0 quad_perm:1 bank_mask:0x1 bound_ctrl:0
+// VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xf1]
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] bank_mask:0x1 bound_ctrl:0
 
 //===----------------------------------------------------------------------===//
 // Check VOP1 opcodes
 //===----------------------------------------------------------------------===//
 // ToDo: v_nop
 
 // NOSICI: error:
 // VI: v_cvt_u32_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1]