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[AMDGPU] Assembler: SOP* instruction fixes
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Authored by nhaustov on Mar 10 2016, 6:15 AM.

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Summary

s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit.
s_rfe_b64 has just one destination operand and no source.
Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that.
Add s_memrealtime test and change comments in smem.s to follow common style.
Change test for s_memtime to use non-zero register to make it really test encoding.
Add tests for s_buffer_load*.
Add tests for SOPC instructions (same for SI and VI)

Diff Detail

Repository
rL LLVM

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nhaustov updated this revision to Diff 50269.Mar 10 2016, 6:15 AM
nhaustov retitled this revision from to [AMDGPU] Assembler: SOP* instruction fixes.
nhaustov updated this object.
nhaustov added a subscriber: llvm-commits.
vpykhtin edited edge metadata.Mar 10 2016, 6:42 AM

LGTM.

May be it worth to add disassembler tests now, at least for SMEM vi.

vpykhtin accepted this revision.Mar 10 2016, 7:06 AM
vpykhtin edited edge metadata.
This revision is now accepted and ready to land.Mar 10 2016, 7:06 AM
This revision was automatically updated to reflect the committed changes.