[ELF] - Fixed handling R_X86_64_DTPOFF64 relocation relaxation

[grimar]

Summary

R_X86_64_DTPOFF64 was not handled properly.
Next sample app was impossible to link before this patch:

~/pg/release/bin/clang -target x86_64-pc-linux testthread.cpp -c -g
~/pg/d+a/bin/ld.lld testthread.o
"Unknown TLS optimization" (value was 17)

__thread int x = 0;
void _start() {
}

It works fine now.

[ruiu]

ELF/Target.cpp

958–963

Can't you reach this piece of code without going through relaxTls, can you?

If that's the case, please move this piece of code to relaxTls.

[grimar]

• Addressed review comments.

ELF/Target.cpp

964–969

Done.

[ruiu]

ELF/Target.cpp

896–900

I guess this is the same? Please inline the code here in a follow-up patch.

900

Does checkInt<64> do anything? A 64-bit integer is always within 64 bits.

[grimar]

• Addressed review comments

ELF/Target.cpp

896–900

Yes, looks so, will do that tomorrow.

900

You right.
Its implementation even has the opt-check for that.

inline bool isInt(int64_t x) {
  return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
}

[ruiu]

LGTM

[grimar]

ELF/Target.cpp

896–900

So after closer look, that is a different situation. We can reach R_X86_64_TPOFF32 from code outside relaxTls.
tls.s testcase for example shows it:

movl %fs:a@tpoff, %eax

generates R_X86_64_TPOFF32 and we reach it from common flow: relocate()->relocateOne().

[grimar]

ELF/Target.cpp

958–963

So in this patch - yes, but I found the way to reach R_X86_64_TPOFF64 using the next code:

.global a
.section .tbss,"awT",@nobits
  .align 4
a:
  .long 0

.text
.globl _start
_start:
 .quad	a@tpoff

But that is also not supported by gold:
gold: error: testthread.o: unexpected reloc 18 in object file
(bfd works fine here)

So it seems compilers don't do that and there is no need to support it.

ELF/Target.cpp

 // relocation target, relocations immediately follow the TLS relocation (which
 // would be applied to rewritten instructions) may have to be skipped.
 // This function returns a number of relocations that need to be skipped.
 size_t X86_64TargetInfo::relaxTls(uint8_t *Loc, uint8_t *BufEnd, uint32_t Type,
                                   uint64_t P, uint64_t SA,
                                   const SymbolBody *S) const {
   switch (Type) {
   case R_X86_64_DTPOFF32:
     relocateOne(Loc, BufEnd, R_X86_64_TPOFF32, P, SA);
     return 0;
+  case R_X86_64_DTPOFF64:
+    relocateOne(Loc, BufEnd, R_X86_64_TPOFF64, P, SA);
+    return 0;
   case R_X86_64_GOTTPOFF:
     relocateTlsIeToLe(Loc, BufEnd, P, SA);
     return 0;
   case R_X86_64_TLSGD: {
     if (canBePreempted(S))
       relocateTlsGdToIe(Loc, BufEnd, P, SA);
     else
       relocateTlsGdToLe(Loc, BufEnd, P, SA);
case R_X86_64_SIZE64:
     write64le(Loc, ZA);
     break;
   case R_X86_64_TPOFF32: {
     uint64_t Val = SA - Out<ELF64LE>::TlsPhdr->p_memsz;
     checkInt<32>(Val, Type);
     write32le(Loc, Val);
     break;
   }
+  case R_X86_64_TPOFF64: {
+    uint64_t Val = SA - Out<ELF64LE>::TlsPhdr->p_memsz;
+    checkInt<64>(Val, Type);
+    write64le(Loc, Val);
+    break;
+  }
   default:
     fatal("unrecognized reloc " + Twine(Type));
   }
 }
 
 // Relocation masks following the #lo(value), #hi(value), #ha(value),
 // #higher(value), #highera(value), #highest(value), and #highesta(value)
 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
 // document.
 static uint16_t applyPPCLo(uint64_t V) { return V; }
 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; }
 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; }
 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; }
 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; }

test/ELF/tls-opt.s

 // DISASM-NEXT: 11077: 48 8d 88 f8 ff ff ff                leaq -8(%rax), %rcx
 // DISASM-NEXT: 1107e: 66 66 66 64 48 8b 04 25 00 00 00 00 movq %fs:0, %rax
 // DISASM-NEXT: 1108a: 48 8d 88 fc ff ff ff                leaq -4(%rax), %rcx
 // GD to LE:
 // DISASM-NEXT: 11091: 64 48 8b 04 25 00 00 00 00          movq %fs:0, %rax
 // DISASM-NEXT: 1109a: 48 8d 80 f8 ff ff ff                leaq -8(%rax), %rax
 // DISASM-NEXT: 110a1: 64 48 8b 04 25 00 00 00 00          movq %fs:0, %rax
 // DISASM-NEXT: 110aa: 48 8d 80 fc ff ff ff                leaq -4(%rax), %rax
+// LD to LE (2):
+// DISASM:      _DTPOFF64_1:
+// DISASM-NEXT: 110b1: f8
+// DISASM:      _DTPOFF64_2:
+// DISASM-NEXT: 110ba: fc
 
 .type tls0,@object
 .section .tbss,"awT",@nobits
 .globl tls0
 .align 4
 tls0:
  .long 0
  .size tls0, 4

  .word 0x6666
  rex64
  call __tls_get_addr@plt
  .byte 0x66
  leaq tls1@tlsgd(%rip),%rdi
  .word 0x6666
  rex64
  call __tls_get_addr@plt
+ 
+ //LD to LE (2):
+_DTPOFF64_1:
+ .quad tls0@DTPOFF
+ nop
+
+_DTPOFF64_2:
+ .quad tls1@DTPOFF
+ nop