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[X86][SSE] Simplify vector LOAD + EXTEND on pre-SSE41 hardware

Authored by RKSimon on Mar 7 2016, 7:43 AM.



Improve vector extension of vectors on hardware without dedicated VSEXT/VZEXT instructions.

We already convert these to SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG but can further improve this by using the legalizer instead of prematurely splitting into legal vectors in the combine as this only properly helps for lowering to VSEXT/VZEXT.

Removes a lot of unnecessary any_extend + mask pattern - (Fix for PR25718).

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RKSimon updated this revision to Diff 49963.Mar 7 2016, 7:43 AM
RKSimon retitled this revision from to [X86][SSE] Simplify vector LOAD + EXTEND on pre-SSE41 hardware.
RKSimon updated this object.
RKSimon added reviewers: congh, qcolombet, spatel.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
qcolombet added inline comments.Mar 9 2016, 2:33 PM
938 ↗(On Diff #49963)


940 ↗(On Diff #49963)

Could you rephrase, I admit I understood the comment after I understood the code :).

944 ↗(On Diff #49963)

Something saying that we build the mask that takes the high element of the low input perhaps?

What through me off for the understanding, at first, here was the name of the variable LoVT. It is not obvious that LoVT is the type of the destination LoVT, not the type of the input LoVT. I guess it does not hurt to use DestLoVT as opposed to InLoVT, instead of LoVT vs. InLoVT.

That being said, up to you, I am fine with the current version, but try to improve the comment :).

RKSimon updated this revision to Diff 50433.Mar 11 2016, 7:50 AM

Update based on Quentin's feedback.

qcolombet accepted this revision.Mar 11 2016, 7:53 AM
qcolombet edited edge metadata.

Hi Simon,



This revision is now accepted and ready to land.Mar 11 2016, 7:53 AM
This revision was automatically updated to reflect the committed changes.