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Differential D17888

[AMDGPU] Assembler: Fix s_setpc_b64
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Authored by nhaustov on Mar 4 2016, 7:18 AM.

Details

Reviewers
• tstellarAMD
arsenm
Commits
rG8e3f099497f1: [AMDGPU] Assembler: Fix s_setpc_b64
rL263005: [AMDGPU] Assembler: Fix s_setpc_b64
Summary

s_setpc_b64 has just one 64-bit source which is the address of instruction to jump to.

Diff Detail

Event Timeline

nhaustov updated this revision to Diff 49826.Mar 4 2016, 7:18 AM
nhaustov retitled this revision from to [AMDGPU] Assembler: Fix s_setpc_b64.
nhaustov updated this object.
nhaustov added reviewers: • tstellarAMD, arsenm.
nhaustov added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptMar 4 2016, 7:18 AM
• tstellarAMD accepted this revision.Mar 4 2016, 7:38 AM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Mar 4 2016, 7:38 AM
Closed by commit rL263005: [AMDGPU] Assembler: Fix s_setpc_b64 (authored by nhaustov). · Explain WhyMar 9 2016, 3:01 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
2 lines
test/
MC/
AMDGPU/
4 lines

Diff 49826

lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Linesdefm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a, 0x17>, "s_sext_i32_i16",
[(set i32:$dst, (sext_inreg i32:$src0, i16))] [(set i32:$dst, (sext_inreg i32:$src0, i16))]
>; >;
defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>; defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>;
defm S_BITSET0_B64 : SOP1_64 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>; defm S_BITSET0_B64 : SOP1_64 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>;
defm S_BITSET1_B32 : SOP1_32 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>; defm S_BITSET1_B32 : SOP1_32 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>;
defm S_BITSET1_B64 : SOP1_64 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>; defm S_BITSET1_B64 : SOP1_64 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>;
defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>; defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>;
defm S_SETPC_B64 : SOP1_64 <sop1<0x20, 0x1d>, "s_setpc_b64", []>; defm S_SETPC_B64 : SOP1_1 <sop1<0x20, 0x1d>, "s_setpc_b64", []>;
defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>; defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>;
defm S_RFE_B64 : SOP1_64 <sop1<0x22, 0x1f>, "s_rfe_b64", []>; defm S_RFE_B64 : SOP1_64 <sop1<0x22, 0x1f>, "s_rfe_b64", []>;
let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in { let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {
defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>; defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>;
defm S_OR_SAVEEXEC_B64 : SOP1_64 <sop1<0x25, 0x21>, "s_or_saveexec_b64", []>; defm S_OR_SAVEEXEC_B64 : SOP1_64 <sop1<0x25, 0x21>, "s_or_saveexec_b64", []>;
defm S_XOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x26, 0x22>, "s_xor_saveexec_b64", []>; defm S_XOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x26, 0x22>, "s_xor_saveexec_b64", []>;
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test/MC/AMDGPU/sop1.s

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
// CHECK: s_bitset1_b32 s1, s2 ; encoding: [0x02,0x1d,0x81,0xbe] // CHECK: s_bitset1_b32 s1, s2 ; encoding: [0x02,0x1d,0x81,0xbe]
s_bitset1_b64 s[2:3], s[4:5] s_bitset1_b64 s[2:3], s[4:5]
// CHECK: s_bitset1_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1e,0x82,0xbe] // CHECK: s_bitset1_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1e,0x82,0xbe]
s_getpc_b64 s[2:3] s_getpc_b64 s[2:3]
// CHECK: s_getpc_b64 s[2:3] ; encoding: [0x00,0x1f,0x82,0xbe] // CHECK: s_getpc_b64 s[2:3] ; encoding: [0x00,0x1f,0x82,0xbe]
s_setpc_b64 s[2:3], s[4:5] s_setpc_b64 s[4:5]
// CHECK: s_setpc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x20,0x82,0xbe] // CHECK: s_setpc_b64 s[4:5] ; encoding: [0x04,0x20,0x80,0xbe]
s_swappc_b64 s[2:3], s[4:5] s_swappc_b64 s[2:3], s[4:5]
// CHECK: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x21,0x82,0xbe] // CHECK: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x21,0x82,0xbe]
s_rfe_b64 s[2:3], s[4:5] s_rfe_b64 s[2:3], s[4:5]
// CHECK: s_rfe_b64 s[2:3], s[4:5] ; encoding: [0x04,0x22,0x82,0xbe] // CHECK: s_rfe_b64 s[2:3], s[4:5] ; encoding: [0x04,0x22,0x82,0xbe]
s_and_saveexec_b64 s[2:3], s[4:5] s_and_saveexec_b64 s[2:3], s[4:5]
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