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Differential D17647

Legalize FNEG on PPC when possible
ClosedPublic

Authored by amehsan on Feb 26 2016, 8:55 AM.

Details

Reviewers
kbarton
nemanjai
Summary

Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has native support for this opcode

Diff Detail

Event Timeline

amehsan updated this revision to Diff 49193.Feb 26 2016, 8:55 AM
amehsan retitled this revision from to Legalize FNEG on PPC when possible.
amehsan updated this object.
amehsan added reviewers: kbarton, nemanjai.
amehsan added a subscriber: llvm-commits.
kbarton edited edge metadata.Feb 26 2016, 1:31 PM

LGTM

kbarton accepted this revision.Feb 26 2016, 1:31 PM
kbarton edited edge metadata.
This revision is now accepted and ready to land.Feb 26 2016, 1:31 PM
kbarton closed this revision.Feb 26 2016, 2:04 PM

Committed r262079

Revision Contents

PathSize
lib/
Target/
PowerPC/
3 lines
test/
CodeGen/
PowerPC/
33 lines

Diff 49193

lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 641 Lines • ▼ Show 20 Lines if (Subtarget.hasVSX()) {
// Vector operation legalization checks the result type of // Vector operation legalization checks the result type of
// SIGN_EXTEND_INREG, overall legalization checks the inner type. // SIGN_EXTEND_INREG, overall legalization checks the inner type.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
} }
if (Subtarget.hasP8Altivec()) { if (Subtarget.hasP8Altivec()) {
addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass); addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass); addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
} }
} }
▲ Show 20 Lines • Show All 10,920 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/vec_fneg.ll

; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubfp ; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s -check-prefix=CHECK-NOVSX
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
; RUN: -mattr=+altivec -mattr=+vsx | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s \
; RUN: -check-prefix=CHECK-NOVSX
define void @t(<4 x float>* %A) { define void @test_float(<4 x float>* %A) {
; CHECK-LABEL: test_float
; CHECK-NOVSX-LABEL: test_float
%tmp2 = load <4 x float>, <4 x float>* %A %tmp2 = load <4 x float>, <4 x float>* %A
%tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2 %tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2
store <4 x float> %tmp3, <4 x float>* %A store <4 x float> %tmp3, <4 x float>* %A
ret void ret void
; CHECK: xvnegsp
; CHECK: blr
; CHECK-NOVSX: vsubfp
; CHECK-NOVSX: blr
}
define void @test_double(<2 x double>* %A) {
; CHECK-LABEL: test_double
; CHECK-NOVSX-LABEL: test_double
%tmp2 = load <2 x double>, <2 x double>* %A
%tmp3 = fsub <2 x double> < double -0.000000e+00, double -0.000000e+00 >, %tmp2
store <2 x double> %tmp3, <2 x double>* %A
ret void
; CHECK: xvnegdp
; CHECK: blr
; CHECK-NOVSX: fneg
; CHECK-NOVSX: fneg
; CHECK-NOVSX: blr
} }