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Differential D17291

[mips] Range check uimm6_lsl2.
ClosedPublic

Authored by dsanders on Feb 16 2016, 7:25 AM.

Details

Reviewers
vkalintiris
Commits
rG19b7f76afa31: [mips] Range check uimm6_lsl2.
rL263419: [mips] Range check uimm6_lsl2.
Summary

Depends on D16811

Diff Detail

Event Timeline

dsanders updated this revision to Diff 48069.Feb 16 2016, 7:25 AM
dsanders retitled this revision from to [mips] Range check uimm6_lsl2..
dsanders updated this object.
dsanders added a reviewer: vkalintiris.
dsanders added a parent revision: D16811: [mips] Range check simm4..
dsanders added a subscriber: llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptFeb 16 2016, 7:25 AM
dsanders updated this revision to Diff 49384.Feb 29 2016, 9:07 AM

Rebase and ping

dsanders added a child revision: D17723: [mips] Simplify ordering of range checked immediate classes..Feb 29 2016, 9:18 AM
vkalintiris accepted this revision.Mar 7 2016, 3:52 AM
vkalintiris edited edge metadata.

LGTM.

We can merge the functionality of several template functions by merging them into a bigger one with more template parameters (or by checking their value). This is not required for this patch, it would be nice to keep in mind though.

This revision is now accepted and ready to land.Mar 7 2016, 3:52 AM
dsanders closed this revision.Mar 14 2016, 4:21 AM

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
13 lines
Disassembler/
42 lines
5 lines
15 lines
test/
MC/
Mips/
6 lines
micromips/
3 lines
micromips32r6/
6 lines
micromips64r6/
6 lines

Diff 49384

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 1,849 Lines • ▼ Show 20 Lines switch (Inst.getOpcode()) {
Opnd = Inst.getOperand(2); Opnd = Inst.getOperand(2);
if (!Opnd.isImm()) if (!Opnd.isImm())
return Error(IDLoc, "expected immediate operand kind"); return Error(IDLoc, "expected immediate operand kind");
Imm = Opnd.getImm(); Imm = Opnd.getImm();
if (!(Imm == 1 || Imm == -1 || if (!(Imm == 1 || Imm == -1 ||
((Imm % 4 == 0) && Imm < 28 && Imm > 0))) ((Imm % 4 == 0) && Imm < 28 && Imm > 0)))
return Error(IDLoc, "immediate operand value out of range"); return Error(IDLoc, "immediate operand value out of range");
break; break;
case Mips::ADDIUR1SP_MM:
Opnd = Inst.getOperand(1);
if (!Opnd.isImm())
return Error(IDLoc, "expected immediate operand kind");
Imm = Opnd.getImm();
if (OffsetToAlignment(Imm, 4LL))
return Error(IDLoc, "misaligned immediate operand value");
if (Imm < 0 || Imm > 255)
return Error(IDLoc, "immediate operand value out of range");
break;
case Mips::ANDI16_MM: case Mips::ANDI16_MM:
Opnd = Inst.getOperand(2); Opnd = Inst.getOperand(2);
if (!Opnd.isImm()) if (!Opnd.isImm())
return Error(IDLoc, "expected immediate operand kind"); return Error(IDLoc, "expected immediate operand kind");
Imm = Opnd.getImm(); Imm = Opnd.getImm();
if (!(Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || if (!(Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535)) Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535))
▲ Show 20 Lines • Show All 1,884 Lines • ▼ Show 20 Lines case Match_UImm5_Lsl2:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected both 7-bit unsigned immediate and multiple of 4"); "expected both 7-bit unsigned immediate and multiple of 4");
case Match_UImmRange2_64: case Match_UImmRange2_64:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range 2 .. 64"); "expected immediate in range 2 .. 64");
case Match_UImm6_0: case Match_UImm6_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 6-bit unsigned immediate"); "expected 6-bit unsigned immediate");
case Match_UImm6_Lsl2:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected both 8-bit unsigned immediate and multiple of 4");
case Match_SImm6_0: case Match_SImm6_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 6-bit signed immediate"); "expected 6-bit signed immediate");
case Match_UImm7_0: case Match_UImm7_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 7-bit unsigned immediate"); "expected 7-bit unsigned immediate");
case Match_UImm8_0: case Match_UImm8_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
▲ Show 20 Lines • Show All 2,574 Lines • Show Last 20 Lines

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Show First 20 Lines • Show All 356 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
unsigned Value, unsigned Value,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeLiSimm7(MCInst &Inst, static DecodeStatus DecodeLiSimm7(MCInst &Inst,
unsigned Value, unsigned Value,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
unsigned Value, unsigned Value,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeSimm16(MCInst &Inst, static DecodeStatus DecodeSimm16(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
template <unsigned Bits, int Offset, int Scale>
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
uint64_t Address,
const void *Decoder);
template <unsigned Bits, int Offset> template <unsigned Bits, int Offset>
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
uint64_t Address, const void *Decoder); uint64_t Address,
const void *Decoder) {
return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
Decoder);
}
template <unsigned Bits, int Offset = 0> template <unsigned Bits, int Offset = 0>
static DecodeStatus DecodeSImmWithOffset(MCInst &Inst, unsigned Value, static DecodeStatus DecodeSImmWithOffset(MCInst &Inst, unsigned Value,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeInsSize(MCInst &Inst, static DecodeStatus DecodeInsSize(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
/// handle. /// handle.
template <typename InsnType> template <typename InsnType>
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
const void *Decoder); const void *Decoder);
▲ Show 20 Lines • Show All 1,470 Lines • ▼ Show 20 Lines if (Value == 0)
Inst.addOperand(MCOperand::createImm(1)); Inst.addOperand(MCOperand::createImm(1));
else if (Value == 0x7) else if (Value == 0x7)
Inst.addOperand(MCOperand::createImm(-1)); Inst.addOperand(MCOperand::createImm(-1));
else else
Inst.addOperand(MCOperand::createImm(Value << 2)); Inst.addOperand(MCOperand::createImm(Value << 2));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder) {
Inst.addOperand(MCOperand::createImm(Value << 2));
return MCDisassembler::Success;
}
static DecodeStatus DecodeLiSimm7(MCInst &Inst, static DecodeStatus DecodeLiSimm7(MCInst &Inst,
unsigned Value, unsigned Value,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (Value == 0x7F) if (Value == 0x7F)
Inst.addOperand(MCOperand::createImm(-1)); Inst.addOperand(MCOperand::createImm(-1));
else else
Inst.addOperand(MCOperand::createImm(Value)); Inst.addOperand(MCOperand::createImm(Value));
Show All 11 Lines
static DecodeStatus DecodeSimm16(MCInst &Inst, static DecodeStatus DecodeSimm16(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn))); Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
template <unsigned Bits, int Offset> template <unsigned Bits, int Offset, int Scale>
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
Value &= ((1 << Bits) - 1); Value &= ((1 << Bits) - 1);
Value *= Scale;
Inst.addOperand(MCOperand::createImm(Value + Offset)); Inst.addOperand(MCOperand::createImm(Value + Offset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
template <unsigned Bits, int Offset> template <unsigned Bits, int Offset>
static DecodeStatus DecodeSImmWithOffset(MCInst &Inst, unsigned Value, static DecodeStatus DecodeSImmWithOffset(MCInst &Inst, unsigned Value,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
// Insn must be >= 0, since it is unsigned that condition is always true. // Insn must be >= 0, since it is unsigned that condition is always true.
assert(Insn < 16); assert(Insn < 16);
int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
255, 32768, 65535}; 255, 32768, 65535};
Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::createImm(Insn << 2));
return MCDisassembler::Success;
}
static DecodeStatus DecodeRegListOperand(MCInst &Inst, static DecodeStatus DecodeRegListOperand(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
Mips::S6, Mips::S7, Mips::FP}; Mips::S6, Mips::S7, Mips::FP};
unsigned RegNum; unsigned RegNum;
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

lib/Target/Mips/MicroMipsInstrInfo.td

def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>; def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>; def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
def simm7 : Operand<i32>; def simm7 : Operand<i32>;
def li_simm7 : Operand<i32> { def li_simm7 : Operand<i32> {
let DecoderMethod = "DecodeLiSimm7"; let DecoderMethod = "DecodeLiSimm7";
} }
def simm12 : Operand<i32> { def simm12 : Operand<i32> {
let DecoderMethod = "DecodeSimm12"; let DecoderMethod = "DecodeSimm12";
} }
def uimm6_lsl2 : Operand<i32> {
let EncoderMethod = "getUImm6Lsl2Encoding";
let DecoderMethod = "DecodeUImm6Lsl2";
}
def simm9_addiusp : Operand<i32> { def simm9_addiusp : Operand<i32> {
let EncoderMethod = "getSImm9AddiuspValue"; let EncoderMethod = "getSImm9AddiuspValue";
let DecoderMethod = "DecodeSimm9SP"; let DecoderMethod = "DecodeSimm9SP";
} }
def uimm3_shift : Operand<i32> { def uimm3_shift : Operand<i32> {
let EncoderMethod = "getUImm3Mod8Encoding"; let EncoderMethod = "getUImm3Mod8Encoding";
let DecoderMethod = "DecodePOOL16BEncodedField"; let DecoderMethod = "DecodePOOL16BEncodedField";
▲ Show 20 Lines • Show All 1,006 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 436 Lines • ▼ Show 20 Lines
def UImm16AsmOperandClass def UImm16AsmOperandClass
: UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>; : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
def ConstantUImm10AsmOperandClass def ConstantUImm10AsmOperandClass
: ConstantUImmAsmOperandClass<10, [UImm16AsmOperandClass]>; : ConstantUImmAsmOperandClass<10, [UImm16AsmOperandClass]>;
def ConstantUImm8AsmOperandClass def ConstantUImm8AsmOperandClass
: ConstantUImmAsmOperandClass<8, [ConstantUImm10AsmOperandClass]>; : ConstantUImmAsmOperandClass<8, [ConstantUImm10AsmOperandClass]>;
def ConstantUImm7AsmOperandClass def ConstantUImm7AsmOperandClass
: ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass]>; : ConstantUImmAsmOperandClass<7, [ConstantUImm8AsmOperandClass]>;
def ConstantUImm6Lsl2AsmOperandClass : AsmOperandClass {
let Name = "UImm6Lsl2";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isScaledUImm<6, 2>";
let SuperClasses = [ConstantUImm7AsmOperandClass];
let DiagnosticType = "UImm6_Lsl2";
}
def ConstantUImm6AsmOperandClass def ConstantUImm6AsmOperandClass
: ConstantUImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>; : ConstantUImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
def ConstantSImm6AsmOperandClass def ConstantSImm6AsmOperandClass
: ConstantSImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>; : ConstantSImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
def ConstantUImm5Plus1AsmOperandClass def ConstantUImm5Plus1AsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 1>; : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 1>;
def ConstantUImm5_Range2_64AsmOperandClass def ConstantUImm5_Range2_64AsmOperandClass
: ConstantUImmRangeAsmOperandClass<2, 64, [ConstantUImm6AsmOperandClass]>; : ConstantUImmRangeAsmOperandClass<2, 64, [ConstantUImm6AsmOperandClass]>;
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
def uimm5_plus32_normalize : Operand<i32> { def uimm5_plus32_normalize : Operand<i32> {
let PrintMethod = "printUImm<5>"; let PrintMethod = "printUImm<5>";
let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
} }
def uimm5_lsl2 : Operand<OtherVT> { def uimm5_lsl2 : Operand<OtherVT> {
let EncoderMethod = "getUImm5Lsl2Encoding"; let EncoderMethod = "getUImm5Lsl2Encoding";
let DecoderMethod = "DecodeUImm5lsl2"; let DecoderMethod = "DecodeUImmWithOffsetAndScale<5, 0, 4>";
let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass; let ParserMatchClass = ConstantUImm5Lsl2AsmOperandClass;
} }
def uimm5_plus32_normalize_64 : Operand<i64> { def uimm5_plus32_normalize_64 : Operand<i64> {
let PrintMethod = "printUImm<5>"; let PrintMethod = "printUImm<5>";
let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
} }
def uimm6_lsl2 : Operand<OtherVT> {
let EncoderMethod = "getUImm6Lsl2Encoding";
let DecoderMethod = "DecodeUImmWithOffsetAndScale<6, 0, 4>";
let ParserMatchClass = ConstantUImm6Lsl2AsmOperandClass;
}
foreach I = {16} in foreach I = {16} in
def uimm # I : Operand<i32> { def uimm # I : Operand<i32> {
let PrintMethod = "printUImm<16>"; let PrintMethod = "printUImm<16>";
let ParserMatchClass = let ParserMatchClass =
!cast<AsmOperandClass>("UImm" # I # "AsmOperandClass"); !cast<AsmOperandClass>("UImm" # I # "AsmOperandClass");
} }
// Like uimm16_64 but coerces simm16 to uimm16. // Like uimm16_64 but coerces simm16 to uimm16.
▲ Show 20 Lines • Show All 1,776 Lines • Show Last 20 Lines

test/MC/Mips/micromips-invalid.s

# RUN: not llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips 2>%t1 # RUN: not llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
addiur1sp $7, 260 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $7, 241 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: misaligned immediate operand value addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $8, 240 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addu16 $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction addu16 $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
subu16 $5, $16, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction subu16 $5, $16, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
andi16 $16, $10, 0x1f # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction andi16 $16, $10, 0x1f # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
andi16 $16, $2, 17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range andi16 $16, $2, 17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
not16 $18, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction not16 $18, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
or16 $16, $10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction or16 $16, $10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

test/MC/Mips/micromips/invalid.s

# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
Show All 30 Lines

test/MC/Mips/micromips32r6/invalid.s

# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
addiur1sp $7, 260 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $7, 241 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: misaligned immediate operand value addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $8, 240 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
beqzc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction beqzc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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test/MC/Mips/micromips64r6/invalid.s

# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
addiur1sp $7, 260 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $7, 241 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: misaligned immediate operand value addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $8, 240 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
beqzc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction beqzc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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