TableGen: Constrain inputs of reg_sequence to be same type

[arsenm]

ping

[arsenm]

ping

[arsenm]

ping

[arsenm]

ping

[ab]

No objection; looks like AMDGPU is the only user of REG_SEQUENCE in patterns ;)

I think the various ARM DAGToDAG also all use the same type.

utils/TableGen/CodeGenDAGPatterns.cpp

1887

TP.error() and return false?

Move this out of the if(I>1) so that it also checks the first child?

utils/TableGen/CodeGenDAGPatterns.cpp

if (getOperator()->getName() == "INSERT_SUBREG") {
         return false;
       }
 
       if (NChild % 2 == 0) {
         TP.error("REG_SEQUENCE requires an odd number of operands!");
         return false;
       }
 
+      // TODO: Should verify that the output register size matches N * the input
+      // size.
+
       if (!isOperandClass(getChild(0), "RegisterClass")) {
         TP.error("REG_SEQUENCE requires a RegisterClass for first operand!");
         return false;
       }
 
       for (unsigned I = 1; I < NChild; I += 2) {
         TreePatternNode *SubIdxChild = getChild(I + 1);
         if (!isOperandClass(SubIdxChild, "SubRegIndex")) {
           TP.error("REG_SEQUENCE requires a SubRegIndex for operand " +
                    itostr(I + 1) + "!");
           return false;
         }
+
+        if (I > 1) {
+          assert(getChild(I)->getNumTypes() == 1 && "FIXME: Unhandled");
+          MadeChange |= getChild(I)->UpdateNodeType(0, getChild(1)->getExtType(0), TP);
+        }
       }
     }
 
     unsigned ChildNo = 0;
     for (unsigned i = 0, e = Inst.getNumOperands(); i != e; ++i) {
       Record *OperandNode = Inst.getOperand(i);
 
       // If the instruction expects a predicate or optional def operand, we