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AMDGPU: Re-visit nodes in performAndCombine
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Authored by arsenm on Feb 12 2016, 12:22 PM.

Reviewers

• tstellarAMD

Summary

This fixes test regressions when i64 loads/stores are made promote.

arsenm retitled this revision from to AMDGPU: Re-visit nodes in performAndCombine.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

LGTM.

This revision is now accepted and ready to land.Feb 12 2016, 12:30 PM

r267240

Path

Size

lib/

Target/

AMDGPU/

5 lines

Show First 20 Lines • Show All 2,299 Lines • ▼ Show 20 Lines	SDValue AMDGPUTargetLowering::performAndCombine(SDNode *N,
std::tie(Lo, Hi) = split64BitValue(N->getOperand(0), DAG);		std::tie(Lo, Hi) = split64BitValue(N->getOperand(0), DAG);

SDValue LoRHS = DAG.getConstant(Lo_32(Val), SL, MVT::i32);		SDValue LoRHS = DAG.getConstant(Lo_32(Val), SL, MVT::i32);
SDValue HiRHS = DAG.getConstant(Hi_32(Val), SL, MVT::i32);		SDValue HiRHS = DAG.getConstant(Hi_32(Val), SL, MVT::i32);

SDValue LoAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Lo, LoRHS);		SDValue LoAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Lo, LoRHS);
SDValue HiAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, HiRHS);		SDValue HiAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, HiRHS);

		// Re-visit the ands. It's possible we eliminated one of them and it could
		// simplify the vector.
		DCI.AddToWorklist(Lo.getNode());
		DCI.AddToWorklist(Hi.getNode());

SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, LoAnd, HiAnd);		SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, LoAnd, HiAnd);
return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);		return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
}		}

SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,		SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
DAGCombinerInfo &DCI) const {		DAGCombinerInfo &DCI) const {
if (N->getValueType(0) != MVT::i64)		if (N->getValueType(0) != MVT::i64)
return SDValue();		return SDValue();
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