Add C intrinsics for Intel SHA Extensions

[benlangmuir]

Summary

This patch adds C intrinsics for the Intel SHA Extensions.

[echristo]

LGTM.

[craig.topper]

Need to enable sse2 feature if -msha is specified. This is currently being done for aes/pclmul.

Also need to disable sha if -mno-sse2 is specified. I just fixed this for aes/pclmul. They were broken in a recent refactoring.

[benlangmuir]

Make feature 'sha' depend on sse2, and disable sha when disabling sse2.

[craig.topper]

LGTM

[echristo]

Craig is good enough, but if you'd like my stamp then here it is :)

[benlangmuir]

Committed as r190999.

include/clang/Basic/BuiltinsX86.def

 // BMI2
 BUILTIN(__builtin_ia32_bzhi_si, "UiUiUi", "")
 BUILTIN(__builtin_ia32_bzhi_di, "ULLiULLiULLi", "")
 BUILTIN(__builtin_ia32_pdep_si, "UiUiUi", "")
 BUILTIN(__builtin_ia32_pdep_di, "ULLiULLiULLi", "")
 BUILTIN(__builtin_ia32_pext_si, "UiUiUi", "")
 BUILTIN(__builtin_ia32_pext_di, "ULLiULLiULLi", "")
 
+// SHA
+BUILTIN(__builtin_ia32_sha1rnds4, "V4iV4iV4iIc", "")
+BUILTIN(__builtin_ia32_sha1nexte, "V4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha1msg1, "V4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha1msg2, "V4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha256rnds2, "V4iV4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha256msg1, "V4iV4iV4i", "")
+BUILTIN(__builtin_ia32_sha256msg2, "V4iV4iV4i", "")
+
 // FMA4
 BUILTIN(__builtin_ia32_vfmaddps, "V4fV4fV4fV4f", "")
 BUILTIN(__builtin_ia32_vfmaddpd, "V2dV2dV2dV2d", "")
 BUILTIN(__builtin_ia32_vfmaddss, "V4fV4fV4fV4f", "")
 BUILTIN(__builtin_ia32_vfmaddsd, "V2dV2dV2dV2d", "")
 BUILTIN(__builtin_ia32_vfmsubps, "V4fV4fV4fV4f", "")
 BUILTIN(__builtin_ia32_vfmsubpd, "V2dV2dV2dV2d", "")
 BUILTIN(__builtin_ia32_vfmsubss, "V4fV4fV4fV4f", "")

include/clang/Driver/Options.td

 def mno_popcnt : Flag<["-"], "mno-popcnt">, Group<m_x86_Features_Group>;
 def mno_fma4 : Flag<["-"], "mno-fma4">, Group<m_x86_Features_Group>;
 def mno_fma : Flag<["-"], "mno-fma">, Group<m_x86_Features_Group>;
 def mno_xop : Flag<["-"], "mno-xop">, Group<m_x86_Features_Group>;
 def mno_f16c : Flag<["-"], "mno-f16c">, Group<m_x86_Features_Group>;
 def mno_rtm : Flag<["-"], "mno-rtm">, Group<m_x86_Features_Group>;
 def mno_prfchw : Flag<["-"], "mno-prfchw">, Group<m_x86_Features_Group>;
 def mno_rdseed : Flag<["-"], "mno-rdseed">, Group<m_x86_Features_Group>;
+def mno_sha : Flag<["-"], "mno-sha">, Group<m_x86_Features_Group>;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_arm_Features_Group>,
   HelpText<"Allow memory accesses to be unaligned (ARM only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group<m_arm_Features_Group>,
   HelpText<"Force all memory accesses to be aligned (ARM only)">;
 def mstrict_align : Flag<["-"], "mstrict-align">, Alias<mno_unaligned_access>, Flags<[CC1Option,HelpHidden]>,
   HelpText<"Force all memory accesses to be aligned (ARM only, same as mno-unaligned-access)">;
 def mno_thumb : Flag<["-"], "mno-thumb">, Group<m_arm_Features_Group>;

 def mpopcnt : Flag<["-"], "mpopcnt">, Group<m_x86_Features_Group>;
 def mfma4 : Flag<["-"], "mfma4">, Group<m_x86_Features_Group>;
 def mfma : Flag<["-"], "mfma">, Group<m_x86_Features_Group>;
 def mxop : Flag<["-"], "mxop">, Group<m_x86_Features_Group>;
 def mf16c : Flag<["-"], "mf16c">, Group<m_x86_Features_Group>;
 def mrtm : Flag<["-"], "mrtm">, Group<m_x86_Features_Group>;
 def mprfchw : Flag<["-"], "mprfchw">, Group<m_x86_Features_Group>;
 def mrdseed : Flag<["-"], "mrdseed">, Group<m_x86_Features_Group>;
+def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
 def mips16 : Flag<["-"], "mips16">, Group<m_Group>;
 def mno_mips16 : Flag<["-"], "mno-mips16">, Group<m_Group>;
 def mmicromips : Flag<["-"], "mmicromips">, Group<m_Group>;
 def mno_micromips : Flag<["-"], "mno-micromips">, Group<m_Group>;
 def mxgot : Flag<["-"], "mxgot">, Group<m_Group>;
 def mno_xgot : Flag<["-"], "mno-xgot">, Group<m_Group>;
 def mldc1_sdc1 : Flag<["-"], "mldc1-sdc1">, Group<m_Group>;
 def mno_ldc1_sdc1 : Flag<["-"], "mno-ldc1-sdc1">, Group<m_Group>;

lib/Basic/Targets.cpp

class X86TargetInfo : public TargetInfo {
   bool HasBMI2;
   bool HasPOPCNT;
   bool HasRTM;
   bool HasPRFCHW;
   bool HasRDSEED;
   bool HasFMA;
   bool HasF16C;
   bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
+  bool HasSHA;
 
   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
   ///
   /// Each enumeration represents a particular CPU supported by Clang. These
   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
   enum CPUKind {
     CK_Generic,
 

 
 public:
   X86TargetInfo(const llvm::Triple &Triple)
       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
         HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
         HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasFMA(false),
         HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
-        HasAVX512PF(false), CPU(CK_Generic), FPMath(FP_Default) {
+        HasAVX512PF(false), HasSHA(false), CPU(CK_Generic), FPMath(FP_Default) {
     BigEndian = false;
     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
   }
   virtual unsigned getFloatEvalMethod() const {
     // X87 evaluates with 80 bits "long double" precision.
     return SSELevel == NoSSE ? 2 : 0;
   }
   virtual void getTargetBuiltins(const Builtin::Info *&Records,
if (Feature == "avx512er") {
       continue;
     }
 
     if (Feature == "avx512pf") {
       HasAVX512PF = true;
       continue;
     }
 
+    if (Feature == "sha") {
+      HasSHA = true;
+      continue;
+    }
+
     assert(Features[i][0] == '+' && "Invalid target feature!");
     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
       .Case("avx512f", AVX512F)
       .Case("avx2", AVX2)
       .Case("avx", AVX)
       .Case("sse4.2", SSE42)
       .Case("sse4.1", SSE41)
       .Case("ssse3", SSSE3)
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
 
   if (HasAVX512CD)
     Builder.defineMacro("__AVX512CD__");
   if (HasAVX512ER)
     Builder.defineMacro("__AVX512ER__");
   if (HasAVX512PF)
     Builder.defineMacro("__AVX512PF__");
 
+  if (HasSHA)
+    Builder.defineMacro("__SHA__");
+
   // Each case falls through to the previous one here.
   switch (SSELevel) {
   case AVX512F:
     Builder.defineMacro("__AVX512F__");
   case AVX2:
     Builder.defineMacro("__AVX2__");
   case AVX:
     Builder.defineMacro("__AVX__");
return llvm::StringSwitch<bool>(Feature)
       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
       .Case("mmx", MMX3DNowLevel >= MMX)
       .Case("pclmul", HasPCLMUL)
       .Case("popcnt", HasPOPCNT)
       .Case("rtm", HasRTM)
       .Case("prfchw", HasPRFCHW)
       .Case("rdseed", HasRDSEED)
+      .Case("sha", HasSHA)
       .Case("sse", SSELevel >= SSE1)
       .Case("sse2", SSELevel >= SSE2)
       .Case("sse3", SSELevel >= SSE3)
       .Case("ssse3", SSELevel >= SSSE3)
       .Case("sse4.1", SSELevel >= SSE41)
       .Case("sse4.2", SSELevel >= SSE42)
       .Case("sse4a", XOPLevel >= SSE4A)
       .Case("x86", true)

lib/Headers/CMakeLists.txt

set(files
   mmintrin.h
   mm_malloc.h
   nmmintrin.h
   pmmintrin.h
   popcntintrin.h
   prfchwintrin.h
   rdseedintrin.h
   rtmintrin.h
+  shaintrin.h
   smmintrin.h
   stdalign.h
   stdarg.h
   stdbool.h
   stddef.h
   stdint.h
   stdnoreturn.h
   tgmath.h

lib/Headers/shaintrin.h

+/*===---- shaintrin.h - SHA intrinsics -------------------------------------===
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __X86INTRIN_H
+#error "Never use <shaintrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef __SHAINTRIN_H
+#define __SHAINTRIN_H
+
+#if !defined (__SHA__)
+#  error "SHA instructions not enabled"
+#endif
+
+#define _mm_sha1rnds4_epu32(V1, V2, M) __extension__ ({ \
+  __builtin_ia32_sha1rnds4((V1), (V2), (M)); })
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha1nexte_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha1nexte(__X, __Y);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha1msg1_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha1msg1(__X, __Y);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha1msg2_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha1msg2(__X, __Y);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha256rnds2_epu32(__m128i __X, __m128i __Y, __m128i __Z)
+{
+  return __builtin_ia32_sha256rnds2(__X, __Y, __Z);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha256msg1_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha256msg1(__X, __Y);
+}
+
+static __inline__ __m128i __attribute__((__always_inline__, __nodebug__))
+_mm_sha256msg2_epu32(__m128i __X, __m128i __Y)
+{
+  return __builtin_ia32_sha256msg2(__X, __Y);
+}
+
+#endif /* __SHAINTRIN_H */

lib/Headers/x86intrin.h

 #ifdef __XOP__
 #include <xopintrin.h>
 #endif
 
 #ifdef __F16C__
 #include <f16cintrin.h>
 #endif
 
+ #ifdef __SHA__
+ #include <shaintrin.h>
+ #endif
+
 // FIXME: LWP
 
 #endif /* __X86INTRIN_H */

test/CodeGen/builtins-x86.c

#ifdef USE_3DNOW
   tmp_V2f = __builtin_ia32_pi2fd(tmp_V2i);
   tmp_V4s = __builtin_ia32_pmulhrw(tmp_V4s, tmp_V4s);
   tmp_V2i = __builtin_ia32_pf2iw(tmp_V2f);
   tmp_V2f = __builtin_ia32_pfnacc(tmp_V2f, tmp_V2f);
   tmp_V2f = __builtin_ia32_pfpnacc(tmp_V2f, tmp_V2f);
   tmp_V2f = __builtin_ia32_pi2fw(tmp_V2i);
   tmp_V2f = __builtin_ia32_pswapdsf(tmp_V2f);
   tmp_V2i = __builtin_ia32_pswapdsi(tmp_V2i);
+
+  tmp_V4i = __builtin_ia32_sha1rnds4(tmp_V4i, tmp_V4i, imm_i);
+  tmp_V4i = __builtin_ia32_sha1nexte(tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha1msg1(tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha1msg2(tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha256rnds2(tmp_V4i, tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha256msg1(tmp_V4i, tmp_V4i);
+  tmp_V4i = __builtin_ia32_sha256msg2(tmp_V4i, tmp_V4i);
 #endif
 }

test/CodeGen/sha-builtins.c

+// RUN: %clang_cc1 %s -O3 -triple=x86_64-unknown-unknown -target-feature +sha -emit-llvm -o - | FileCheck %s
+
+// Don't include mm_malloc.h, it's system specific.
+#define __MM_MALLOC_H
+
+#include <x86intrin.h>
+
+__m128i test_sha1rnds4(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha1rnds4
+  return _mm_sha1rnds4_epu32(a, b, 8);
+}
+__m128i test_sha1nexte(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha1nexte
+  return _mm_sha1nexte_epu32(a, b);
+}
+__m128i test_sha1msg1(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha1msg1
+  return _mm_sha1msg1_epu32(a, b);
+}
+__m128i test_sha1msg2(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha1msg2
+  return _mm_sha1msg2_epu32(a, b);
+}
+__m128i test_sha256rnds2(__m128i a, __m128i b, __m128i c) {
+  // CHECK: call <4 x i32> @llvm.x86.sha256rnds2
+  return _mm_sha256rnds2_epu32(a, b, c);
+}
+__m128i test_sha256msg1(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha256msg1
+  return _mm_sha256msg1_epu32(a, b);
+}
+__m128i test_sha256msg2(__m128i a, __m128i b) {
+  // CHECK: call <4 x i32> @llvm.x86.sha256msg2
+  return _mm_sha256msg2_epu32(a, b);
+}
 No newline at end of file

test/Preprocessor/x86_target_features.c

 
 // F16C: #define __AVX__ 1
 // F16C: #define __F16C__ 1
 
 // RUN: %clang -target i386-unknown-unknown -march=atom -mf16c -mno-avx -x c -E -dM -o - %s | FileCheck --check-prefix=F16CNOAVX %s
 
 // F16CNOAVX-NOT: #define __AVX__ 1
 // F16CNOAVX-NOT: #define __F16C__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -msha -x c -E -dM -o - %s | FileCheck --check-prefix=SHA %s
+
+// SHA: #define __SHA__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -msha -mno-sha -x c -E -dM -o - %s | FileCheck --check-prefix=SHANOSHA %s
+
+// SHANOSHA-NOT: #define __SHA__ 1