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[X86][AVX] Add support for 64-bit VZEXT_LOAD of 256-bit vectors to EltsFromConsecutiveLoads
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Authored by RKSimon on Feb 1 2016, 6:28 AM.

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Summary

This patch enables 64-bit VZEXT_LOAD of 256-bit vectors.

Follow up to D16217 and D16729

This change uncovered an odd pattern where VZEXT_LOAD v4i64 was being lowered to a load of the lower v2i64 (so the 2nd i64 destination element wasn't being zeroed), I can't find any use/reason for this and have removed the pattern and replaced it so only the 1st i64 element is loaded and the upper bits all zeroed. This matches the description for X86ISD::VZEXT_LOAD

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon updated this revision to Diff 46529.Feb 1 2016, 6:28 AM
RKSimon retitled this revision from to [X86][AVX] Add support for 64-bit VZEXT_LOAD of 256-bit vectors to EltsFromConsecutiveLoads.
RKSimon updated this object.
RKSimon added reviewers: delena, spatel, mkuper.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
delena added inline comments.Feb 1 2016, 7:09 AM
lib/Target/X86/X86ISelLowering.cpp
5644 ↗(On Diff #46529)

Could you, please, add 512 bit vector here?

lib/Target/X86/X86InstrSSE.td
5061 ↗(On Diff #46529)

The same pattern should be added to X86InstAVX512.td, right?

RKSimon updated this revision to Diff 46630.Feb 2 2016, 1:39 AM

Added 512-bit vector support

delena accepted this revision.Feb 2 2016, 12:30 PM
delena edited edge metadata.

Thank you.
LGTM

lib/Target/X86/X86ISelLowering.cpp
5645 ↗(On Diff #46630)

v8i64 is always legal for 512-bit vector.

This revision is now accepted and ready to land.Feb 2 2016, 12:30 PM
This revision was automatically updated to reflect the committed changes.

Thanks Elena - as this can get run before legalization I've left the 8f64 legality test in.